cb135f59b8
This patch translates all IOAPIC interrupts into MSI ones. One pseudo ioapic address space is added to transfer the MSI message. By default, it will be system memory address space. When IR is enabled, it will be IOMMU address space. Currently, only emulated IOAPIC is supported. Idea suggested by Jan Kiszka and Rita Sinha in the following patch: https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
32 lines
661 B
C
32 lines
661 B
C
#ifndef HW_APIC_MSIDEF_H
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#define HW_APIC_MSIDEF_H
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/*
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* Intel APIC constants: from include/asm/msidef.h
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*/
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/*
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* Shifts for MSI data
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*/
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#define MSI_DATA_VECTOR_SHIFT 0
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#define MSI_DATA_VECTOR_MASK 0x000000ff
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#define MSI_DATA_DELIVERY_MODE_SHIFT 8
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#define MSI_DATA_LEVEL_SHIFT 14
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#define MSI_DATA_TRIGGER_SHIFT 15
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/*
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* Shift/mask fields for msi address
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*/
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#define MSI_ADDR_DEST_MODE_SHIFT 2
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#define MSI_ADDR_REDIRECTION_SHIFT 3
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#define MSI_ADDR_DEST_ID_SHIFT 12
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#define MSI_ADDR_DEST_IDX_SHIFT 4
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
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#endif /* HW_APIC_MSIDEF_H */
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