Leon Alrae bf7910c6b1 target-mips: move PREF, CACHE, LLD and SCD instructions
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
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Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org

- QEMU team
Description
A fork of QEMU-Nyx which is better suited for my bachelors thesis
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