508280f566
Update our copy of libvixl to upstream's 1.5 release. This includes the upstream versions of the fixes we were carrying locally (commit ffebe899). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1407162987-4659-1-git-send-email-peter.maydell@linaro.org
84 lines
3.1 KiB
C++
84 lines
3.1 KiB
C++
// Copyright 2013, ARM Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef VIXL_CPU_A64_H
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#define VIXL_CPU_A64_H
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#include "globals.h"
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#include "instructions-a64.h"
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namespace vixl {
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class CPU {
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public:
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// Initialise CPU support.
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static void SetUp();
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// Ensures the data at a given address and with a given size is the same for
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// the I and D caches. I and D caches are not automatically coherent on ARM
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// so this operation is required before any dynamically generated code can
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// safely run.
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static void EnsureIAndDCacheCoherency(void *address, size_t length);
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// Handle tagged pointers.
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template <typename T>
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static T SetPointerTag(T pointer, uint64_t tag) {
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VIXL_ASSERT(is_uintn(kAddressTagWidth, tag));
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// Use C-style casts to get static_cast behaviour for integral types (T),
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// and reinterpret_cast behaviour for other types.
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uint64_t raw = (uint64_t)pointer;
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VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw));
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raw = (raw & ~kAddressTagMask) | (tag << kAddressTagOffset);
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return (T)raw;
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}
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template <typename T>
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static uint64_t GetPointerTag(T pointer) {
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// Use C-style casts to get static_cast behaviour for integral types (T),
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// and reinterpret_cast behaviour for other types.
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uint64_t raw = (uint64_t)pointer;
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VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw));
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return (raw & kAddressTagMask) >> kAddressTagOffset;
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}
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private:
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// Return the content of the cache type register.
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static uint32_t GetCacheType();
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// I and D cache line size in bytes.
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static unsigned icache_line_size_;
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static unsigned dcache_line_size_;
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};
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} // namespace vixl
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#endif // VIXL_CPU_A64_H
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