0ce265ffef
Templatize the address_space_* and *_phys functions, so that we can add similar functions in the next patch that work with a lightweight, cache-like version of address_space_map/unmap. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
112 lines
3.4 KiB
C
112 lines
3.4 KiB
C
#ifndef CPU_COMMON_H
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#define CPU_COMMON_H
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/* CPU interfaces that are target independent. */
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#ifndef CONFIG_USER_ONLY
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#include "exec/hwaddr.h"
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#endif
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#include "qemu/bswap.h"
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#include "qemu/queue.h"
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#include "qemu/fprintf-fn.h"
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/**
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* CPUListState:
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* @cpu_fprintf: Print function.
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* @file: File to print to using @cpu_fprint.
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*
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* State commonly used for iterating over CPU models.
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*/
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typedef struct CPUListState {
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fprintf_function cpu_fprintf;
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FILE *file;
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} CPUListState;
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/* The CPU list lock nests outside tb_lock/tb_unlock. */
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void qemu_init_cpu_list(void);
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void cpu_list_lock(void);
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void cpu_list_unlock(void);
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#if !defined(CONFIG_USER_ONLY)
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enum device_endian {
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DEVICE_NATIVE_ENDIAN,
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DEVICE_BIG_ENDIAN,
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DEVICE_LITTLE_ENDIAN,
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};
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/* address in the RAM (different from a physical address) */
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#if defined(CONFIG_XEN_BACKEND)
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typedef uint64_t ram_addr_t;
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# define RAM_ADDR_MAX UINT64_MAX
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# define RAM_ADDR_FMT "%" PRIx64
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#else
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typedef uintptr_t ram_addr_t;
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# define RAM_ADDR_MAX UINTPTR_MAX
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# define RAM_ADDR_FMT "%" PRIxPTR
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#endif
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extern ram_addr_t ram_size;
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/* memory API */
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typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
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void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
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/* This should not be used by devices. */
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ram_addr_t qemu_ram_addr_from_host(void *ptr);
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RAMBlock *qemu_ram_block_by_name(const char *name);
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RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
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ram_addr_t *offset);
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void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
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void qemu_ram_unset_idstr(RAMBlock *block);
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const char *qemu_ram_get_idstr(RAMBlock *rb);
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size_t qemu_ram_pagesize(RAMBlock *block);
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void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
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int len, int is_write);
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static inline void cpu_physical_memory_read(hwaddr addr,
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void *buf, int len)
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{
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cpu_physical_memory_rw(addr, buf, len, 0);
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}
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static inline void cpu_physical_memory_write(hwaddr addr,
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const void *buf, int len)
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{
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cpu_physical_memory_rw(addr, (void *)buf, len, 1);
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}
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void *cpu_physical_memory_map(hwaddr addr,
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hwaddr *plen,
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int is_write);
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void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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int is_write, hwaddr access_len);
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void cpu_register_map_client(QEMUBH *bh);
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void cpu_unregister_map_client(QEMUBH *bh);
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bool cpu_physical_memory_is_io(hwaddr phys_addr);
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/* Coalesced MMIO regions are areas where write operations can be reordered.
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* This usually implies that write operations are side-effect free. This allows
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* batching which can make a major impact on performance when using
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* virtualization.
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*/
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void qemu_flush_coalesced_mmio_buffer(void);
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void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
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const uint8_t *buf, int len);
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void cpu_flush_icache_range(hwaddr start, int len);
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extern struct MemoryRegion io_mem_rom;
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extern struct MemoryRegion io_mem_notdirty;
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typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
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ram_addr_t offset, ram_addr_t length, void *opaque);
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int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
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#endif
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#endif /* CPU_COMMON_H */
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