Kwok Cheung Yeung ea3164aafc linux-user: Fix MIPS ISA transitions during signal handling
Processors supporting the MIPS16 or microMIPS ISAs set bit 0 in target
addresses to indicate that the target is written using a compressed ISA.

During signal handling, when jumping to or returning from a signal
handler, bit 0 of the destination PC is inspected and MIPS_HFLAG_M16 in
hflags cleared or set accordingly.  Bit 0 of the PC is then cleared.

Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-20 18:16:17 +02:00
..
2012-12-19 08:31:31 +01:00
2012-03-14 22:20:24 +01:00
2012-12-19 08:31:31 +01:00
2012-08-14 20:26:55 +01:00
2010-10-05 13:53:56 -05:00