d2123ead89
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3479 c046a42c-6fe2-441c-8c8c-71466251a162
470 lines
18 KiB
C
470 lines
18 KiB
C
/*
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* MIPS emulation for qemu: CPU initialisation routines.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2007 Herve Poussineau
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* CPU / CPU family specific config register values. */
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/* Have config1, is MIPS32R1, uses TLB, no virtual icache,
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uncached coherency */
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#define MIPS_CONFIG0 \
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((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
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(0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
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(0x2 << CP0C0_K0))
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/* Have config2, no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, no FPU */
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr,
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no external interrupt controller, no vectored interupts,
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no 1kb pages, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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(0 << CP0C3_SM) | (0 << CP0C3_TL))
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/* Define a implementation number of 1.
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Define a major version 1, minor version 0. */
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#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
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struct mips_def_t {
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const unsigned char *name;
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int32_t CP0_PRid;
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int32_t CP0_Config0;
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int32_t CP0_Config1;
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int32_t CP0_Config2;
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int32_t CP0_Config3;
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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int32_t SYNCI_Step;
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int32_t CCRes;
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int32_t CP0_Status_rw_bitmask;
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_SRSCtl;
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int32_t CP1_fcr0;
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int32_t SEGBITS;
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int32_t CP0_SRSConf0_rw_bitmask;
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int32_t CP0_SRSConf0;
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int32_t CP0_SRSConf1_rw_bitmask;
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int32_t CP0_SRSConf1;
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int32_t CP0_SRSConf2_rw_bitmask;
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int32_t CP0_SRSConf2;
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int32_t CP0_SRSConf3_rw_bitmask;
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int32_t CP0_SRSConf3;
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int32_t CP0_SRSConf4_rw_bitmask;
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int32_t CP0_SRSConf4;
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int insn_flags;
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};
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/*****************************************************************************/
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/* MIPS CPU definitions */
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static mips_def_t mips_defs[] =
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{
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{
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.name = "4Kc",
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.CP0_PRid = 0x00018000,
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.CP0_Config0 = MIPS_CONFIG0,
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16,
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},
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{
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.name = "4KEcR1",
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.CP0_PRid = 0x00018400,
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.CP0_Config0 = MIPS_CONFIG0,
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16,
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},
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{
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.name = "4KEc",
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.CP0_PRid = 0x00019000,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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},
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{
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.name = "24Kc",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x1278FF1F,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
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},
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{
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.name = "24Kf",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
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},
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{
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.name = "34Kf",
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.CP0_PRid = 0x00019500,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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/* No DSP implemented. */
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.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
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(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
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(0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
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(1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
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(0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
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(0xff << CP0TCSt_TASID),
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
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.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
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.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
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(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
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.CP0_SRSConf1_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
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(0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
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.CP0_SRSConf2_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
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(0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
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.CP0_SRSConf3_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
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(0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
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.CP0_SRSConf4_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
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(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
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},
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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{
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.name = "R4000",
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.CP0_PRid = 0x00000400,
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 16,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x3678FFFF,
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/* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
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.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 40,
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.insn_flags = CPU_MIPS3,
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},
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{
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.name = "5Kc",
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.CP0_PRid = 0x00018100,
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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.CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
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(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
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(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x32F8FFFF,
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.SEGBITS = 42,
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.insn_flags = CPU_MIPS64,
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},
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{
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.name = "5Kf",
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.CP0_PRid = 0x00018100,
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
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(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
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(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x36F8FFFF,
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/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
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.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
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(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 42,
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.insn_flags = CPU_MIPS64,
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},
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{
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.name = "20Kc",
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/* We emulate a later version of the 20Kc, earlier ones had a broken
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WAIT instruction. */
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.CP0_PRid = 0x000182a0,
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
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(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
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(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x36FBFFFF,
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/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
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.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
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(1 << FCR0_D) | (1 << FCR0_S) |
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(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 40,
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.insn_flags = CPU_MIPS64 | ASE_MIPS3D,
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},
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{
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/* A generic CPU providing MIPS64 Release 2 features.
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FIXME: Eventually this should be replaced by a real CPU model. */
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.name = "MIPS64R2-generic",
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.CP0_PRid = 0x00000000,
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
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(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
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(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x36FBFFFF,
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.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 40,
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.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
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},
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#endif
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};
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int mips_find_by_name (const unsigned char *name, mips_def_t **def)
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{
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int i, ret;
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ret = -1;
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*def = NULL;
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for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
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if (strcasecmp(name, mips_defs[i].name) == 0) {
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*def = &mips_defs[i];
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ret = 0;
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break;
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}
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}
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return ret;
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}
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void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
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{
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int i;
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for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
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(*cpu_fprintf)(f, "MIPS '%s'\n",
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mips_defs[i].name);
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}
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}
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#ifndef CONFIG_USER_ONLY
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static void no_mmu_init (CPUMIPSState *env, mips_def_t *def)
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{
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env->tlb->nb_tlb = 1;
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env->tlb->map_address = &no_mmu_map_address;
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}
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static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def)
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{
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env->tlb->nb_tlb = 1;
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env->tlb->map_address = &fixed_mmu_map_address;
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}
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static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def)
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{
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env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
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env->tlb->map_address = &r4k_map_address;
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env->tlb->do_tlbwi = r4k_do_tlbwi;
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env->tlb->do_tlbwr = r4k_do_tlbwr;
|
|
env->tlb->do_tlbp = r4k_do_tlbp;
|
|
env->tlb->do_tlbr = r4k_do_tlbr;
|
|
}
|
|
|
|
static void mmu_init (CPUMIPSState *env, mips_def_t *def)
|
|
{
|
|
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
|
|
|
|
/* There are more full-featured MMU variants in older MIPS CPUs,
|
|
R3000, R6000 and R8000 come to mind. If we ever support them,
|
|
this check will need to look up a different place than those
|
|
newfangled config registers. */
|
|
switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
|
|
case 0:
|
|
no_mmu_init(env, def);
|
|
break;
|
|
case 1:
|
|
r4k_mmu_init(env, def);
|
|
break;
|
|
case 3:
|
|
fixed_mmu_init(env, def);
|
|
break;
|
|
default:
|
|
cpu_abort(env, "MMU type not supported\n");
|
|
}
|
|
env->CP0_Random = env->tlb->nb_tlb - 1;
|
|
env->tlb->tlb_in_use = env->tlb->nb_tlb;
|
|
}
|
|
#endif /* CONFIG_USER_ONLY */
|
|
|
|
static void fpu_init (CPUMIPSState *env, mips_def_t *def)
|
|
{
|
|
env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
|
|
|
|
env->fpu->fcr0 = def->CP1_fcr0;
|
|
#ifdef CONFIG_USER_ONLY
|
|
if (env->CP0_Config1 & (1 << CP0C1_FP))
|
|
env->hflags |= MIPS_HFLAG_FPU;
|
|
if (env->fpu->fcr0 & (1 << FCR0_F64))
|
|
env->hflags |= MIPS_HFLAG_F64;
|
|
#endif
|
|
}
|
|
|
|
static void mvp_init (CPUMIPSState *env, mips_def_t *def)
|
|
{
|
|
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
|
|
|
|
/* MVPConf1 implemented, TLB sharable, no gating storage support,
|
|
programmable cache partitioning implemented, number of allocatable
|
|
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
|
|
implemented, 5 TCs implemented. */
|
|
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
|
|
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
|
|
#ifndef CONFIG_USER_ONLY
|
|
/* Usermode has no TLB support */
|
|
(env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
|
|
#endif
|
|
// TODO: actually do 2 VPEs.
|
|
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
|
|
// (0x04 << CP0MVPC0_PTC);
|
|
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
|
|
(0x04 << CP0MVPC0_PTC);
|
|
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
|
|
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
|
|
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
|
|
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
|
|
(0x1 << CP0MVPC1_PCP1);
|
|
}
|
|
|
|
int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
|
|
{
|
|
if (!def)
|
|
def = env->cpu_model;
|
|
if (!def)
|
|
cpu_abort(env, "Unable to find MIPS CPU definition\n");
|
|
env->cpu_model = def;
|
|
env->CP0_PRid = def->CP0_PRid;
|
|
env->CP0_Config0 = def->CP0_Config0;
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
env->CP0_Config0 |= (1 << CP0C0_BE);
|
|
#endif
|
|
env->CP0_Config1 = def->CP0_Config1;
|
|
env->CP0_Config2 = def->CP0_Config2;
|
|
env->CP0_Config3 = def->CP0_Config3;
|
|
env->CP0_Config6 = def->CP0_Config6;
|
|
env->CP0_Config7 = def->CP0_Config7;
|
|
env->SYNCI_Step = def->SYNCI_Step;
|
|
env->CCRes = def->CCRes;
|
|
env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
|
|
env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
|
|
env->CP0_SRSCtl = def->CP0_SRSCtl;
|
|
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
if (def->insn_flags & ISA_MIPS3)
|
|
{
|
|
env->hflags |= MIPS_HFLAG_64;
|
|
env->SEGBITS = def->SEGBITS;
|
|
env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
|
|
} else {
|
|
env->SEGBITS = 32;
|
|
env->SEGMask = 0xFFFFFFFF;
|
|
}
|
|
#endif
|
|
env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask;
|
|
env->CP0_SRSConf0 = def->CP0_SRSConf0;
|
|
env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask;
|
|
env->CP0_SRSConf1 = def->CP0_SRSConf1;
|
|
env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask;
|
|
env->CP0_SRSConf2 = def->CP0_SRSConf2;
|
|
env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask;
|
|
env->CP0_SRSConf3 = def->CP0_SRSConf3;
|
|
env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask;
|
|
env->CP0_SRSConf4 = def->CP0_SRSConf4;
|
|
env->insn_flags = def->insn_flags;
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
mmu_init(env, def);
|
|
#endif
|
|
fpu_init(env, def);
|
|
mvp_init(env, def);
|
|
return 0;
|
|
}
|