 Peter Crosthwaite
		
	
	
		f7838b5290
		
	
	
	
	arm: cortex-a9: Fix cache-line size and associativity
			Peter Crosthwaite
		
	
	
		f7838b5290
		
	
	
	
	arm: cortex-a9: Fix cache-line size and associativity
		
			
			For A9, The cache associativity is 4 and the lines size is 32B. Self identify in CCSIDR accordingly. Cache size remains at 16k. QEMU doesn't emulate caches, but we should still report the correct cache-line size to the guest. Some guests (like u-boot) complain if the cache-line size mismatches a requested flush or invalidate operation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team
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