4759513bd9
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2800 c046a42c-6fe2-441c-8c8c-71466251a162
209 lines
6.9 KiB
C
209 lines
6.9 KiB
C
/*
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* MIPS emulation for qemu: CPU initialisation routines.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2007 Herve Poussineau
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* CPU / CPU family specific config register values. */
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/* Have config1, is MIPS32R1, uses TLB, no virtual icache,
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uncached coherency */
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#define MIPS_CONFIG0 \
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((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
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(0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
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(0x2 << CP0C0_K0))
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/* Have config2, 64 sets Icache, 16 bytes Icache line,
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2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, no FPU */
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | \
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(0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
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(0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr,
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no external interrupt controller, no vectored interupts,
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no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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(0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
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/* Define a implementation number of 1.
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Define a major version 1, minor version 0. */
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#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
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struct mips_def_t {
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const unsigned char *name;
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int32_t CP0_PRid;
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int32_t CP0_Config0;
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int32_t CP0_Config1;
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int32_t CP0_Config2;
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int32_t CP0_Config3;
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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int32_t SYNCI_Step;
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int32_t CCRes;
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int32_t Status_rw_bitmask;
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int32_t CP1_fcr0;
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};
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/*****************************************************************************/
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/* MIPS CPU definitions */
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static mips_def_t mips_defs[] =
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{
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#ifndef TARGET_MIPS64
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{
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.name = "4Kc",
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.CP0_PRid = 0x00018000,
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.CP0_Config0 = MIPS_CONFIG0,
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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},
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{
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.name = "4KEcR1",
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.CP0_PRid = 0x00018400,
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.CP0_Config0 = MIPS_CONFIG0,
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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},
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{
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.name = "4KEc",
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.CP0_PRid = 0x00019000,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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},
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{
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.name = "24Kc",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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},
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{
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.name = "24Kf",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3678FF17,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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},
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#else
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{
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.name = "R4000",
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.CP0_PRid = 0x00000400,
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.SYNCI_Step = 16,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3678FFFF,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) |
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(0x4 << FCR0_PRID) | (0x0 << FCR0_REV),
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},
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#endif
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};
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int mips_find_by_name (const unsigned char *name, mips_def_t **def)
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{
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int i, ret;
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ret = -1;
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*def = NULL;
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for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
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if (strcasecmp(name, mips_defs[i].name) == 0) {
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*def = &mips_defs[i];
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ret = 0;
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break;
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}
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}
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return ret;
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}
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void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
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{
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int i;
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for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
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(*cpu_fprintf)(f, "MIPS '%s'\n",
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mips_defs[i].name);
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}
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}
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int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
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{
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if (!def)
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cpu_abort(env, "Unable to find MIPS CPU definition\n");
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env->CP0_PRid = def->CP0_PRid;
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#ifdef TARGET_WORDS_BIGENDIAN
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env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
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#else
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env->CP0_Config0 = def->CP0_Config0;
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#endif
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env->CP0_Config1 = def->CP0_Config1;
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env->CP0_Config2 = def->CP0_Config2;
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env->CP0_Config3 = def->CP0_Config3;
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env->CP0_Config6 = def->CP0_Config6;
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env->CP0_Config7 = def->CP0_Config7;
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env->SYNCI_Step = def->SYNCI_Step;
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env->CCRes = def->CCRes;
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env->Status_rw_bitmask = def->Status_rw_bitmask;
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env->fcr0 = def->CP1_fcr0;
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#if defined (MIPS_USES_R4K_TLB)
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env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
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env->CP0_Random = env->nb_tlb - 1;
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env->tlb_in_use = env->nb_tlb;
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#endif
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return 0;
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}
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