iTCO_wdt: mask NMI_NOW bit for update_no_reboot_bit() call
[ Upstream commit daa814d784ac034c62ab3fb0ef83daeafef527e2 ] Commit da23b6faa8bf ("watchdog: iTCO: Add support for Cannon Lake PCH iTCO") does not mask NMI_NOW bit during TCO1_CNT register's value comparison for update_no_reboot_bit() call causing following failure: ... iTCO_vendor_support: vendor-support=0 iTCO_wdt iTCO_wdt: unable to reset NO_REBOOT flag, device disabled by hardware/BIOS ... and this can lead to unexpected NMIs later during regular crashkernel's workflow because of watchdog probe call failures. This change masks NMI_NOW bit for TCO1_CNT register values to avoid unexpected NMI_NOW bit inversions. Fixes: da23b6faa8bf ("watchdog: iTCO: Add support for Cannon Lake PCH iTCO") Signed-off-by: Oleksandr Ocheretnyi <oocheret@cisco.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20240913191403.2560805-1-oocheret@cisco.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -82,6 +82,13 @@
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#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
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#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
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#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
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#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
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/*
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* NMI_NOW is bit 8 of TCO1_CNT register
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* Read/Write
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* This bit is implemented as RW but has no effect on HW.
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*/
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#define NMI_NOW BIT(8)
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/* internal variables */
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/* internal variables */
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struct iTCO_wdt_private {
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struct iTCO_wdt_private {
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struct watchdog_device wddev;
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struct watchdog_device wddev;
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@ -219,13 +226,23 @@ static int update_no_reboot_bit_cnt(void *priv, bool set)
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struct iTCO_wdt_private *p = priv;
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struct iTCO_wdt_private *p = priv;
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u16 val, newval;
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u16 val, newval;
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val = inw(TCO1_CNT(p));
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/*
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* writing back 1b1 to NMI_NOW of TCO1_CNT register
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* causes NMI_NOW bit inversion what consequently does
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* not allow to perform the register's value comparison
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* properly.
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*
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* NMI_NOW bit masking for TCO1_CNT register values
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* helps to avoid possible NMI_NOW bit inversions on
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* following write operation.
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*/
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val = inw(TCO1_CNT(p)) & ~NMI_NOW;
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if (set)
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if (set)
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val |= BIT(0);
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val |= BIT(0);
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else
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else
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val &= ~BIT(0);
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val &= ~BIT(0);
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outw(val, TCO1_CNT(p));
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outw(val, TCO1_CNT(p));
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newval = inw(TCO1_CNT(p));
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newval = inw(TCO1_CNT(p)) & ~NMI_NOW;
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/* make sure the update is successful */
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/* make sure the update is successful */
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return val != newval ? -EIO : 0;
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return val != newval ? -EIO : 0;
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