clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
[ Upstream commit e0f253a52ccee3cf3eb987e99756e20c68a1aac9 ]
To work around a limitation in our clock modelling, we try to force two
bits in the AUDIO0 PLL to 0, in the CCU probe routine.
However the ~ operator only applies to the first expression, and does
not cover the second bit, so we end up clearing only bit 1.
Group the bit-ORing with parentheses, to make it both clearer to read
and actually correct.
Fixes: 35b97bb941
("clk: sunxi-ng: Add support for the D1 SoC clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1360,7 +1360,7 @@ static int sun20i_d1_ccu_probe(struct platform_device *pdev)
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/* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
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val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
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val &= ~BIT(1) | BIT(0);
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val &= ~(BIT(1) | BIT(0));
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writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
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/* Force fanout-27M factor N to 0. */
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