pinctrl: renesas: r8a779g0: Fix (H)SCIF3 suffixes
[ Upstream commit 5350f38150a171322b50c0a48efa671885f87050 ]
(H)SCIF instance 3 has two alternate pin groups: "hscif3" and
"hscif3_a", resp. "scif3" and "scif3_a", but the actual meanings of the
pins within the groups do not match.
Increase uniformity by adopting R-Car V4M naming:
- Rename "hscif3_a" to "hscif3_b",
- Rename "hscif3" to "hscif3_a",
- Rename "scif3" to "scif3_b".
While at it, remove unneeded separators.
Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support")
Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions")
Fixes: 213b713255defaa6 ("pinctrl: renesas: r8a779g0: Add missing HSCIF3_A")
Fixes: 49e4697656bdd1cd ("pinctrl: renesas: r8a779g0: Add missing SCIF3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/61fdde58e369e8070ffd3c5811c089e6219c7ecc.1717754960.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Geert Uytterhoeven
Greg Kroah-Hartman
parent
4153dffff0
commit
c9a80089c6
@ -71,11 +71,11 @@
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#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
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/* GPSR1 */
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#define GPSR1_28 F_(HTX3, IP3SR1_19_16)
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#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
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#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
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#define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
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#define GPSR1_24 F_(HRX3, IP3SR1_3_0)
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#define GPSR1_28 F_(HTX3_A, IP3SR1_19_16)
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#define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12)
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#define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8)
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#define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4)
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#define GPSR1_24 F_(HRX3_A, IP3SR1_3_0)
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#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
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#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
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#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
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@ -295,11 +295,11 @@
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/* SR1 */
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/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -325,11 +325,11 @@
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#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* SR2 */
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/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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@ -770,24 +770,24 @@ static const u16 pinmux_data[] = {
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/* IP0SR1 */
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PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
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PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
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PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
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PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),
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PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),
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PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
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PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A),
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PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
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PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),
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PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),
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PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
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PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A),
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PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
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PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),
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PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),
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PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
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PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
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PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
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PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
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PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
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PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
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PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
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PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
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PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),
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PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),
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PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
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@ -858,25 +858,25 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
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/* IP3SR1 */
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PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
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PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),
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PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
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PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
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PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
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PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
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PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
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PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
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PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
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PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
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PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
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PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),
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PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
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PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
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@ -1642,51 +1642,50 @@ static const unsigned int hscif2_ctrl_mux[] = {
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};
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/* - HSCIF3 ----------------------------------------------------------------- */
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static const unsigned int hscif3_data_pins[] = {
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/* HRX3, HTX3 */
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RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
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};
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static const unsigned int hscif3_data_mux[] = {
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HRX3_MARK, HTX3_MARK,
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};
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static const unsigned int hscif3_clk_pins[] = {
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/* HSCK3 */
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RCAR_GP_PIN(1, 25),
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};
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static const unsigned int hscif3_clk_mux[] = {
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HSCK3_MARK,
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};
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static const unsigned int hscif3_ctrl_pins[] = {
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/* HRTS3_N, HCTS3_N */
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RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
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};
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static const unsigned int hscif3_ctrl_mux[] = {
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HRTS3_N_MARK, HCTS3_N_MARK,
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};
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/* - HSCIF3_A ----------------------------------------------------------------- */
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static const unsigned int hscif3_data_a_pins[] = {
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/* HRX3_A, HTX3_A */
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RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
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RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
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};
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static const unsigned int hscif3_data_a_mux[] = {
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HRX3_A_MARK, HTX3_A_MARK,
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};
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static const unsigned int hscif3_clk_a_pins[] = {
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/* HSCK3_A */
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RCAR_GP_PIN(1, 3),
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RCAR_GP_PIN(1, 25),
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};
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static const unsigned int hscif3_clk_a_mux[] = {
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HSCK3_A_MARK,
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};
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static const unsigned int hscif3_ctrl_a_pins[] = {
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/* HRTS3_N_A, HCTS3_N_A */
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RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
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RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
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};
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static const unsigned int hscif3_ctrl_a_mux[] = {
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HRTS3_N_A_MARK, HCTS3_N_A_MARK,
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};
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static const unsigned int hscif3_data_b_pins[] = {
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/* HRX3_B, HTX3_B */
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RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
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};
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static const unsigned int hscif3_data_b_mux[] = {
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HRX3_B_MARK, HTX3_B_MARK,
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};
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static const unsigned int hscif3_clk_b_pins[] = {
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/* HSCK3_B */
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RCAR_GP_PIN(1, 3),
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};
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static const unsigned int hscif3_clk_b_mux[] = {
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HSCK3_B_MARK,
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};
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static const unsigned int hscif3_ctrl_b_pins[] = {
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/* HRTS3_N_B, HCTS3_N_B */
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RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
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};
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static const unsigned int hscif3_ctrl_b_mux[] = {
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HRTS3_N_B_MARK, HCTS3_N_B_MARK,
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};
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/* - I2C0 ------------------------------------------------------------------- */
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static const unsigned int i2c0_pins[] = {
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/* SDA0, SCL0 */
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@ -2280,29 +2279,6 @@ static const unsigned int scif1_ctrl_b_mux[] = {
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};
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/* - SCIF3 ------------------------------------------------------------------ */
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static const unsigned int scif3_data_pins[] = {
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/* RX3, TX3 */
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RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
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};
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static const unsigned int scif3_data_mux[] = {
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RX3_MARK, TX3_MARK,
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};
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static const unsigned int scif3_clk_pins[] = {
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/* SCK3 */
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RCAR_GP_PIN(1, 4),
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};
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static const unsigned int scif3_clk_mux[] = {
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SCK3_MARK,
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};
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static const unsigned int scif3_ctrl_pins[] = {
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/* RTS3_N, CTS3_N */
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RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
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};
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static const unsigned int scif3_ctrl_mux[] = {
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RTS3_N_MARK, CTS3_N_MARK,
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};
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/* - SCIF3_A ------------------------------------------------------------------ */
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static const unsigned int scif3_data_a_pins[] = {
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/* RX3_A, TX3_A */
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RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
|
||||
@ -2325,6 +2301,28 @@ static const unsigned int scif3_ctrl_a_mux[] = {
|
||||
RTS3_N_A_MARK, CTS3_N_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int scif3_data_b_pins[] = {
|
||||
/* RX3_B, TX3_B */
|
||||
RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
static const unsigned int scif3_data_b_mux[] = {
|
||||
RX3_B_MARK, TX3_B_MARK,
|
||||
};
|
||||
static const unsigned int scif3_clk_b_pins[] = {
|
||||
/* SCK3_B */
|
||||
RCAR_GP_PIN(1, 4),
|
||||
};
|
||||
static const unsigned int scif3_clk_b_mux[] = {
|
||||
SCK3_B_MARK,
|
||||
};
|
||||
static const unsigned int scif3_ctrl_b_pins[] = {
|
||||
/* RTS3_N_B, CTS3_N_B */
|
||||
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int scif3_ctrl_b_mux[] = {
|
||||
RTS3_N_B_MARK, CTS3_N_B_MARK,
|
||||
};
|
||||
|
||||
/* - SCIF4 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif4_data_pins[] = {
|
||||
/* RX4, TX4 */
|
||||
@ -2566,12 +2564,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(hscif2_data),
|
||||
SH_PFC_PIN_GROUP(hscif2_clk),
|
||||
SH_PFC_PIN_GROUP(hscif2_ctrl),
|
||||
SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(hscif3_data_a),
|
||||
SH_PFC_PIN_GROUP(hscif3_clk_a),
|
||||
SH_PFC_PIN_GROUP(hscif3_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(hscif3_data_b),
|
||||
SH_PFC_PIN_GROUP(hscif3_clk_b),
|
||||
SH_PFC_PIN_GROUP(hscif3_ctrl_b),
|
||||
|
||||
SH_PFC_PIN_GROUP(i2c0),
|
||||
SH_PFC_PIN_GROUP(i2c1),
|
||||
@ -2662,12 +2660,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(scif1_data_b),
|
||||
SH_PFC_PIN_GROUP(scif1_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif1_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */
|
||||
SH_PFC_PIN_GROUP(scif3_data_a),
|
||||
SH_PFC_PIN_GROUP(scif3_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif3_ctrl_a),
|
||||
SH_PFC_PIN_GROUP(scif3_data_b),
|
||||
SH_PFC_PIN_GROUP(scif3_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(scif4_data),
|
||||
SH_PFC_PIN_GROUP(scif4_clk),
|
||||
SH_PFC_PIN_GROUP(scif4_ctrl),
|
||||
@ -2791,13 +2789,12 @@ static const char * const hscif2_groups[] = {
|
||||
};
|
||||
|
||||
static const char * const hscif3_groups[] = {
|
||||
/* suffix might be updated */
|
||||
"hscif3_data",
|
||||
"hscif3_clk",
|
||||
"hscif3_ctrl",
|
||||
"hscif3_data_a",
|
||||
"hscif3_clk_a",
|
||||
"hscif3_ctrl_a",
|
||||
"hscif3_data_b",
|
||||
"hscif3_clk_b",
|
||||
"hscif3_ctrl_b",
|
||||
};
|
||||
|
||||
static const char * const i2c0_groups[] = {
|
||||
@ -2967,13 +2964,12 @@ static const char * const scif1_groups[] = {
|
||||
};
|
||||
|
||||
static const char * const scif3_groups[] = {
|
||||
/* suffix might be updated */
|
||||
"scif3_data",
|
||||
"scif3_clk",
|
||||
"scif3_ctrl",
|
||||
"scif3_data_a",
|
||||
"scif3_clk_a",
|
||||
"scif3_ctrl_a",
|
||||
"scif3_data_b",
|
||||
"scif3_clk_b",
|
||||
"scif3_ctrl_b",
|
||||
};
|
||||
|
||||
static const char * const scif4_groups[] = {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user