6e392ff884
[ Upstream commit 8eb8fe67e2c84324398f5983c41b4f831d0705b3 ] The dcache.cva encoding shown in the comments are wrong, it's for dcache.cval1 (which is restricted to L1) instead. Fix this in the comment and in the hardcoded instruction. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guo Ren <guoren@kernel.org> Tested-by: Drew Fustini <dfustini@baylibre.com> Link: https://lore.kernel.org/r/20230912072410.2481-1-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
148 lines
4.5 KiB
C
148 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Sifive.
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*/
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#ifndef ASM_ERRATA_LIST_H
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#define ASM_ERRATA_LIST_H
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#include <asm/alternative.h>
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#include <asm/vendorid_list.h>
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#ifdef CONFIG_ERRATA_SIFIVE
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#define ERRATA_SIFIVE_CIP_453 0
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#define ERRATA_SIFIVE_CIP_1200 1
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#define ERRATA_SIFIVE_NUMBER 2
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#endif
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#ifdef CONFIG_ERRATA_THEAD
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#define ERRATA_THEAD_PBMT 0
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#define ERRATA_THEAD_CMO 1
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#define ERRATA_THEAD_NUMBER 2
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#endif
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#define CPUFEATURE_SVPBMT 0
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#define CPUFEATURE_ZICBOM 1
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#define CPUFEATURE_NUMBER 2
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#ifdef __ASSEMBLY__
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#define ALT_INSN_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
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__stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#define ALT_PAGE_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \
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__stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#else /* !__ASSEMBLY__ */
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#define ALT_FLUSH_TLB_PAGE(x) \
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asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
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ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
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: : "r" (addr) : "memory")
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/*
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* _val is marked as "will be overwritten", so need to set it to 0
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* in the default case.
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*/
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#define ALT_SVPBMT_SHIFT 61
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#define ALT_THEAD_PBMT_SHIFT 59
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#define ALT_SVPBMT(_val, prot) \
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asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
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"li %0, %1\t\nslli %0,%0,%3", 0, \
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CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \
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"li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \
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ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
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: "=r"(_val) \
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: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
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"I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
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"I"(ALT_SVPBMT_SHIFT), \
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"I"(ALT_THEAD_PBMT_SHIFT))
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#ifdef CONFIG_ERRATA_THEAD_PBMT
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/*
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* IO/NOCACHE memory types are handled together with svpbmt,
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* so on T-Head chips, check if no other memory type is set,
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* and set the non-0 PMA type if applicable.
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*/
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#define ALT_THEAD_PMA(_val) \
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asm volatile(ALTERNATIVE( \
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__nops(7), \
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"li t3, %1\n\t" \
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"slli t3, t3, %3\n\t" \
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"and t3, %0, t3\n\t" \
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"bne t3, zero, 2f\n\t" \
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"li t3, %2\n\t" \
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"slli t3, t3, %3\n\t" \
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"or %0, %0, t3\n\t" \
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"2:", THEAD_VENDOR_ID, \
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ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
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: "+r"(_val) \
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: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \
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"I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \
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"I"(ALT_THEAD_PBMT_SHIFT) \
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: "t3")
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#else
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#define ALT_THEAD_PMA(_val)
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#endif
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/*
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* dcache.ipa rs1 (invalidate, physical address)
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* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
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* 0000001 01010 rs1 000 00000 0001011
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* dache.iva rs1 (invalida, virtual address)
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* 0000001 00110 rs1 000 00000 0001011
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*
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* dcache.cpa rs1 (clean, physical address)
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* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
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* 0000001 01001 rs1 000 00000 0001011
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* dcache.cva rs1 (clean, virtual address)
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* 0000001 00101 rs1 000 00000 0001011
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*
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* dcache.cipa rs1 (clean then invalidate, physical address)
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* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
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* 0000001 01011 rs1 000 00000 0001011
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* dcache.civa rs1 (... virtual address)
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* 0000001 00111 rs1 000 00000 0001011
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*
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* sync.s (make sure all cache operations finished)
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* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
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* 0000000 11001 00000 000 00000 0001011
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*/
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#define THEAD_inval_A0 ".long 0x0265000b"
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#define THEAD_clean_A0 ".long 0x0255000b"
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#define THEAD_flush_A0 ".long 0x0275000b"
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#define THEAD_SYNC_S ".long 0x0190000b"
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#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
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asm volatile(ALTERNATIVE_2( \
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__nops(6), \
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"mv a0, %1\n\t" \
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"j 2f\n\t" \
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"3:\n\t" \
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"cbo." __stringify(_op) " (a0)\n\t" \
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"add a0, a0, %0\n\t" \
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"2:\n\t" \
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"bltu a0, %2, 3b\n\t" \
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"nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
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"mv a0, %1\n\t" \
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"j 2f\n\t" \
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"3:\n\t" \
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THEAD_##_op##_A0 "\n\t" \
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"add a0, a0, %0\n\t" \
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"2:\n\t" \
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"bltu a0, %2, 3b\n\t" \
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THEAD_SYNC_S, THEAD_VENDOR_ID, \
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ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
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: : "r"(_cachesize), \
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"r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
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"r"((unsigned long)(_start) + (_size)) \
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: "a0")
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#endif /* __ASSEMBLY__ */
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#endif
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