Komal Bajaj d42364dd66 EDAC/qcom: Correct interrupt enable register configuration ... commit c158647c107358bf1be579f98e4bb705c1953292 upstream. The previous implementation incorrectly configured the cmn_interrupt_2_enable register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag, Data RAM ECC interrupts would lead to issues like double handling of the interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured for interrupts which needs to be handled by EL3. EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable. Fixes: 27450653f1 ("drivers: edac: Add EDAC driver support for QCOM SoCs") Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: <stable@kernel.org> Link: https://lore.kernel.org/r/20241119064608.12326-1-quic_kbajaj@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2025-03-07 16:56:40 +01:00
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al_mc_edac.c
altera_edac.c
altera_edac.h
amd64_edac.c
amd64_edac.h
amd76x_edac.c
amd8111_edac.c
amd8111_edac.h
amd8131_edac.c
amd8131_edac.h
armada_xp_edac.c
aspeed_edac.c
bluefield_edac.c
cell_edac.c
cpc925_edac.c
debugfs.c
dmc520_edac.c
e7xxx_edac.c
e752x_edac.c
edac_device_sysfs.c
edac_device.c
edac_device.h
edac_mc_sysfs.c
edac_mc.c
edac_mc.h
edac_module.c
edac_module.h
edac_pci_sysfs.c
edac_pci.c
edac_pci.h
fsl_ddr_edac.c
fsl_ddr_edac.h
ghes_edac.c
highbank_l2_edac.c
highbank_mc_edac.c
i7core_edac.c
i10nm_base.c
i3000_edac.c
i3200_edac.c
i5000_edac.c
i5100_edac.c
i5400_edac.c
i7300_edac.c
i82443bxgx_edac.c
i82860_edac.c
i82875p_edac.c
i82975x_edac.c
ie31200_edac.c
igen6_edac.c	EDAC/igen6: Avoid segmentation fault on module unload	2024-12-14 19:53:17 +01:00
Kconfig
layerscape_edac.c
Makefile
mce_amd.c
mce_amd.h
mpc85xx_edac.c
mpc85xx_edac.h
octeon_edac-l2c.c
octeon_edac-lmc.c
octeon_edac-pc.c
octeon_edac-pci.c
pasemi_edac.c
pnd2_edac.c
pnd2_edac.h
ppc4xx_edac.c
ppc4xx_edac.h
qcom_edac.c	EDAC/qcom: Correct interrupt enable register configuration	2025-03-07 16:56:40 +01:00
r82600_edac.c
sb_edac.c
sifive_edac.c
skx_base.c
skx_common.c
skx_common.h
synopsys_edac.c
thunderx_edac.c
ti_edac.c
wq.c
x38_edac.c
xgene_edac.c