b60cf8e59e
Fix device tree schema validation error messages for the SiFive
Unmatched: ' cache-sets:0:0: 1024 was expected'.
The existing bindings allow for just 1024 cache-sets but the fu740 on
Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary
power of two, however this is not supported by dt-schema. The RTL for
the IP, to which the number of cache-sets is a tunable parameter, has
been released publicly so speculatively adding a small number of
"reasonable" values seems unwise also.
Instead, as the binding only supports two distinct controllers: add 2048
and explicitly lock it to the fu740's l2 cache while limiting 1024 to
the l2 cache on the fu540.
Fixes: af951c3a11 ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740")
Reported-by: Atul Khare <atulkhare@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220803185359.942928-1-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
128 lines
2.7 KiB
YAML
128 lines
2.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2020 SiFive, Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive L2 Cache Controller
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maintainers:
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- Sagar Kadam <sagar.kadam@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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description:
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The SiFive Level 2 Cache Controller is used to provide access to fast copies
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of memory for masters in a Core Complex. The Level 2 Cache Controller also
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acts as directory-based coherency manager.
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All the properties in ePAPR/DeviceTree specification applies for this platform.
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allOf:
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- $ref: /schemas/cache-controller.yaml#
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select:
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properties:
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compatible:
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contains:
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enum:
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- sifive,fu540-c000-ccache
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- sifive,fu740-c000-ccache
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- sifive,fu540-c000-ccache
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- sifive,fu740-c000-ccache
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- const: cache
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cache-block-size:
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const: 64
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cache-level:
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const: 2
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cache-sets:
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enum: [1024, 2048]
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cache-size:
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const: 2097152
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cache-unified: true
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interrupts:
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minItems: 3
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items:
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- description: DirError interrupt
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- description: DataError interrupt
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- description: DataFail interrupt
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- description: DirFail interrupt
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reg:
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maxItems: 1
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next-level-cache: true
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memory-region:
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maxItems: 1
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description: |
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The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
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The reserved memory node should be defined as per the bindings in reserved-memory.txt.
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if:
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properties:
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compatible:
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contains:
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const: sifive,fu540-c000-ccache
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then:
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properties:
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interrupts:
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description: |
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Must contain entries for DirError, DataError and DataFail signals.
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maxItems: 3
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cache-sets:
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const: 1024
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else:
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properties:
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interrupts:
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description: |
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Must contain entries for DirError, DataError, DataFail, DirFail signals.
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minItems: 4
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cache-sets:
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const: 2048
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additionalProperties: false
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required:
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- compatible
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- cache-block-size
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- cache-level
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- cache-sets
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- cache-size
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- cache-unified
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- interrupts
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- reg
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examples:
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- |
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cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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reg = <0x2010000 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <1>,
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<2>,
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<3>;
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next-level-cache = <&L25>;
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memory-region = <&l2_lim>;
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};
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