edadebb349
commit 1f5e7eb7868e42227ac426c96d437117e6e06e8e upstream.
Tony reported intermittent lockups on poweroff. His analysis identified the
wbinvd() in stop_this_cpu() as the culprit. This was added to ensure that
on SME enabled machines a kexec() does not leave any stale data in the
caches when switching from encrypted to non-encrypted mode or vice versa.
That wbinvd() is conditional on the SME feature bit which is read directly
from CPUID. But that readout does not check whether the CPUID leaf is
available or not. If it's not available the CPU will return the value of
the highest supported leaf instead. Depending on the content the "SME" bit
might be set or not.
That's incorrect but harmless. Making the CPUID readout conditional makes
the observed hangs go away, but it does not fix the underlying problem:
CPU0 CPU1
stop_other_cpus()
send_IPIs(REBOOT); stop_this_cpu()
while (num_online_cpus() > 1); set_online(false);
proceed... -> hang
wbinvd()
WBINVD is an expensive operation and if multiple CPUs issue it at the same
time the resulting delays are even larger.
But CPU0 already observed num_online_cpus() going down to 1 and proceeds
which causes the system to hang.
This issue exists independent of WBINVD, but the delays caused by WBINVD
make it more prominent.
Make this more robust by adding a cpumask which is initialized to the
online CPU mask before sending the IPIs and CPUs clear their bit in
stop_this_cpu() after the WBINVD completed. Check for that cpumask to
become empty in stop_other_cpus() instead of watching num_online_cpus().
The cpumask cannot plug all holes either, but it's better than a raw
counter and allows to restrict the NMI fallback IPI to be sent only the
CPUs which have not reported within the timeout window.
Fixes: 08f253ec37 ("x86/cpu: Clear SME feature flag when not in use")
Reported-by: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Ashok Raj <ashok.raj@intel.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/all/3817d810-e0f1-8ef8-0bbd-663b919ca49b@cybernetics.com
Link: https://lore.kernel.org/r/87h6r770bv.ffs@tglx
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
102 lines
2.3 KiB
C
102 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CPU_H
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#define _ASM_X86_CPU_H
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#include <linux/device.h>
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#include <linux/cpu.h>
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#include <linux/topology.h>
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#include <linux/nodemask.h>
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#include <linux/percpu.h>
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#include <asm/ibt.h>
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#ifdef CONFIG_SMP
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extern void prefill_possible_map(void);
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#else /* CONFIG_SMP */
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static inline void prefill_possible_map(void) {}
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#define cpu_physical_id(cpu) boot_cpu_physical_apicid
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#define cpu_acpi_id(cpu) 0
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#define safe_smp_processor_id() 0
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#endif /* CONFIG_SMP */
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struct x86_cpu {
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struct cpu cpu;
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};
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#ifdef CONFIG_HOTPLUG_CPU
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extern int arch_register_cpu(int num);
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extern void arch_unregister_cpu(int);
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extern void start_cpu0(void);
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#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
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extern int _debug_hotplug_cpu(int cpu, int action);
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#endif
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#endif
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extern void ap_init_aperfmperf(void);
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int mwait_usable(const struct cpuinfo_x86 *);
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unsigned int x86_family(unsigned int sig);
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unsigned int x86_model(unsigned int sig);
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unsigned int x86_stepping(unsigned int sig);
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#ifdef CONFIG_CPU_SUP_INTEL
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extern void __init sld_setup(struct cpuinfo_x86 *c);
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extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);
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extern bool handle_guest_split_lock(unsigned long ip);
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extern void handle_bus_lock(struct pt_regs *regs);
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u8 get_this_hybrid_cpu_type(void);
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#else
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static inline void __init sld_setup(struct cpuinfo_x86 *c) {}
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static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code)
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{
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return false;
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}
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static inline bool handle_guest_split_lock(unsigned long ip)
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{
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return false;
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}
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static inline void handle_bus_lock(struct pt_regs *regs) {}
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static inline u8 get_this_hybrid_cpu_type(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_IA32_FEAT_CTL
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void init_ia32_feat_ctl(struct cpuinfo_x86 *c);
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#else
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static inline void init_ia32_feat_ctl(struct cpuinfo_x86 *c) {}
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#endif
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extern __noendbr void cet_disable(void);
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struct ucode_cpu_info;
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int intel_cpu_collect_info(struct ucode_cpu_info *uci);
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static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1,
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unsigned int s2, unsigned int p2)
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{
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if (s1 != s2)
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return false;
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/* Processor flags are either both 0 ... */
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if (!p1 && !p2)
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return true;
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/* ... or they intersect. */
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return p1 & p2;
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}
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extern u64 x86_read_arch_cap_msr(void);
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extern struct cpumask cpus_stop_mask;
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#endif /* _ASM_X86_CPU_H */
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