298b95f111
Based on the normalized pattern:
this software is distributed under the terms of the gnu general public
license ( gpl ) version 2 as published by the free software foundation
this software is provided by the copyright holders and contributors as
is and any express or implied warranties including but not limited to
the implied warranties of merchantability and fitness for a particular
purpose are disclaimed in no event shall the copyright owner or
contributors be liable for any direct indirect incidental special
exemplary or consequential damages (including but not limited to
procurement of substitute goods or services loss of use data or
profits or business interruption) however caused and on any theory of
liability whether in contract strict liability or tort (including
negligence or otherwise) arising in any way out of the use of this
software even if advised of the possibility of such damage
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* usb-omap.h - Platform data for the various OMAP USB IPs
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com
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*/
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#define OMAP3_HS_USB_PORTS 3
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enum usbhs_omap_port_mode {
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OMAP_USBHS_PORT_MODE_UNUSED,
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OMAP_EHCI_PORT_MODE_PHY,
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OMAP_EHCI_PORT_MODE_TLL,
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OMAP_EHCI_PORT_MODE_HSIC,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
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OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
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};
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struct usbtll_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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};
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struct ehci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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unsigned phy_reset:1;
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};
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struct ohci_hcd_omap_platform_data {
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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unsigned es2_compatibility:1;
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};
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struct usbhs_omap_platform_data {
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int nports;
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enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
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int reset_gpio_port[OMAP3_HS_USB_PORTS];
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struct regulator *regulator[OMAP3_HS_USB_PORTS];
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struct ehci_hcd_omap_platform_data *ehci_data;
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struct ohci_hcd_omap_platform_data *ohci_data;
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/* OMAP3 <= ES2.1 have a single ulpi bypass control bit */
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unsigned single_ulpi_bypass:1;
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unsigned es2_compatibility:1;
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unsigned phy_reset:1;
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};
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/*-------------------------------------------------------------------------*/
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struct omap_musb_board_data {
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u8 interface_type;
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u8 mode;
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u16 power;
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unsigned extvbus:1;
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void (*set_phy_power)(u8 on);
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void (*clear_irq)(void);
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void (*set_mode)(u8 mode);
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void (*reset)(void);
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};
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enum musb_interface {
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MUSB_INTERFACE_ULPI,
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MUSB_INTERFACE_UTMI
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};
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