update j2 support patches to Yoshinori Sato's versions
with some minor fixes. unlike my minimal patches, Sato-san's properly add the isa level logic to binutils and add cas.l atomic intrinsics to gcc.
This commit is contained in:
Rich Felker
parent
69cadffdec
commit
23d6f66966
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@ -1,45 +1,641 @@
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--- binutils-2.25.1.orig/gas/config/tc-sh.c
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diff --git a/bfd/archures.c b/bfd/archures.c
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+++ binutils-2.25.1/gas/config/tc-sh.c
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index 51068b9..c67d76b 100644
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@@ -1730,6 +1730,11 @@
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--- a/bfd/archures.c
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goto fail;
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+++ b/bfd/archures.c
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break;
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@@ -294,10 +294,12 @@ DESCRIPTION
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.#define bfd_mach_sh_dsp 0x2d
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.#define bfd_mach_sh2a 0x2a
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.#define bfd_mach_sh2a_nofpu 0x2b
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+.#define bfd_mach_shj2 0x2c
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.#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
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.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
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.#define bfd_mach_sh2a_or_sh4 0x2a3
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.#define bfd_mach_sh2a_or_sh3e 0x2a4
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+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
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.#define bfd_mach_sh2e 0x2e
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.#define bfd_mach_sh3 0x30
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.#define bfd_mach_sh3_nommu 0x31
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diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
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index ca0cafd..99e92c6 100644
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--- a/bfd/bfd-in2.h
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+++ b/bfd/bfd-in2.h
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@@ -2109,10 +2109,12 @@ enum bfd_architecture
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#define bfd_mach_sh_dsp 0x2d
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#define bfd_mach_sh2a 0x2a
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#define bfd_mach_sh2a_nofpu 0x2b
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+#define bfd_mach_shj2 0x2c
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#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
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#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
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#define bfd_mach_sh2a_or_sh4 0x2a3
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#define bfd_mach_sh2a_or_sh3e 0x2a4
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+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
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#define bfd_mach_sh2e 0x2e
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#define bfd_mach_sh3 0x30
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#define bfd_mach_sh3_nommu 0x31
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diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c
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index d516d66..66d21a5 100644
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--- a/bfd/cpu-sh.c
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+++ b/bfd/cpu-sh.c
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@@ -44,7 +44,9 @@
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#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
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#define SH2A_OR_SH4_NEXT arch_info_struct + 18
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#define SH2A_OR_SH3E_NEXT arch_info_struct + 19
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-#define SH64_NEXT NULL
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+#define SH64_NEXT arch_info_struct + 20
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+#define SHJ2_NEXT arch_info_struct + 21
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+#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
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static const bfd_arch_info_type arch_info_struct[] =
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{
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@@ -348,6 +350,36 @@ static const bfd_arch_info_type arch_info_struct[] =
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bfd_arch_default_fill,
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SH64_NEXT
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},
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+ {
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+ 32, /* 32 bits in a word. */
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+ 32, /* 32 bits in an address. */
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+ 8, /* 8 bits in a byte. */
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+ bfd_arch_sh,
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+ bfd_mach_shj2,
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+ "sh", /* Architecture name. . */
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+ "j2", /* Machine name. */
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+ 1,
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+ FALSE, /* Not the default. */
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+ bfd_default_compatible,
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+ bfd_default_scan,
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+ bfd_arch_default_fill,
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+ SHJ2_NEXT
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+ },
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+ {
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+ 32, /* 32 bits in a word. */
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+ 32, /* 32 bits in an address. */
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+ 8, /* 8 bits in a byte. */
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+ bfd_arch_sh,
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+ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
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+ "sh", /* Architecture name. . */
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+ "sh2a-or-sh3e-or-j2", /* Machine name. */
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+ 1,
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+ FALSE, /* Not the default. */
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+ bfd_default_compatible,
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+ bfd_default_scan,
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+ bfd_arch_default_fill,
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+ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
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+ },
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};
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const bfd_arch_info_type bfd_sh_arch =
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@@ -398,6 +430,8 @@ static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] =
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{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
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{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
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{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
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+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
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+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
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{ 0, 0, 0 } /* Terminator. */
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};
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diff --git a/binutils/readelf.c b/binutils/readelf.c
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index a31db52..5ec21b0 100644
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--- a/binutils/readelf.c
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+++ b/binutils/readelf.c
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@@ -3217,6 +3217,8 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
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case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
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case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
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case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
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+ case EF_SHJ2: strcat (buf, ", j2"); break;
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+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
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default: strcat (buf, _(", unknown ISA")); break;
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}
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diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
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index 125f073..37f6fb0 100644
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--- a/gas/config/tc-sh.c
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+++ b/gas/config/tc-sh.c
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@@ -1648,6 +1648,8 @@ get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand)
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ptr++;
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}
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get_operand (&ptr, operand + 2);
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+ if (strcmp (info->name,"cas") == 0)
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+ operand[2].type = A_IND_0;
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}
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else
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{
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@@ -2187,7 +2189,10 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
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goto fail;
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reg_m = 4;
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break;
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-
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+ case A_IND_0:
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+ case A_IND_0:
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+ if (user->type != A_IND_N || user->reg != 0)
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+ if (user->reg != 0)
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+ goto fail;
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+ goto fail;
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+ break;
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+ break;
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+
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default:
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case A_REG_N:
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printf (_("unhandled %d\n"), arg);
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case A_INC_N:
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goto fail;
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case A_DEC_N:
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diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
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--- binutils-2.25.1.orig/opcodes/sh-dis.c
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index cc29889..a3e18b5 100644
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+++ binutils-2.25.1/opcodes/sh-dis.c
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--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
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@@ -703,6 +703,9 @@
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+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
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case AS_DEC_N:
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@@ -12,8 +12,6 @@
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fprintf_fn (stream, "@-r%d", rn);
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sh2a_nofpu_or_sh3_nommu:
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! Instructions introduced into sh2a-nofpu-or-sh3-nommu
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pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
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- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
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- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
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! Instructions inherited from ancestors: sh sh2
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add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
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diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
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index c702845..812aa76 100644
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--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
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+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
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@@ -12,7 +12,7 @@
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sh2a_nofpu_or_sh4_nommu_nofpu:
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! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
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-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
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+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
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add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
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add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
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addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
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@@ -119,8 +119,8 @@ sh2a_nofpu_or_sh4_nommu_nofpu:
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rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
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rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
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sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
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- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
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- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
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+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
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+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
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shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
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shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
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shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
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diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
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index 6f4a17e..5b38643 100644
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--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
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+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
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@@ -64,7 +64,7 @@ sh2a_nofpu:
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movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
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|
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
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-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
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+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
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add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
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add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
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addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
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|
@@ -171,8 +171,8 @@ sh2a_nofpu:
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|
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
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|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
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|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
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|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
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|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
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+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
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+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
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shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
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shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
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shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
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diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
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index 25c8ae1..69d3536 100644
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--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
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+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
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@@ -13,7 +13,7 @@ sh2a_or_sh3e:
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! Instructions introduced into sh2a-or-sh3e
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||||||
|
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -124,8 +124,8 @@ sh2a_or_sh3e:
|
||||||
|
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||||
|
index d3300ca..c697268 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||||
|
@@ -39,7 +39,7 @@ sh2a_or_sh4:
|
||||||
|
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||||
|
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -150,8 +150,8 @@ sh2a_or_sh4:
|
||||||
|
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh2a.s b/gas/testsuite/gas/sh/arch/sh2a.s
|
||||||
|
index 370dbd4..0d9f3b0 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh2a.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh2a.s
|
||||||
|
@@ -16,7 +16,7 @@ sh2a:
|
||||||
|
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||||
|
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -140,8 +140,8 @@ sh2a:
|
||||||
|
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh3-dsp.s b/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||||
|
index acc26be..cfd4dfe 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||||
|
@@ -12,7 +12,7 @@
|
||||||
|
sh3_dsp:
|
||||||
|
! Instructions introduced into sh3-dsp
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||||
|
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -152,8 +152,8 @@ sh3_dsp:
|
||||||
|
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||||
|
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||||
|
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||||
|
index 3e8ff02..dacaae1 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||||
|
@@ -26,7 +26,7 @@ sh3_nommu:
|
||||||
|
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||||
|
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -133,8 +133,8 @@ sh3_nommu:
|
||||||
|
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh3.s b/gas/testsuite/gas/sh/arch/sh3.s
|
||||||
|
index 97ab939..aa70fc3 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh3.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh3.s
|
||||||
|
@@ -13,7 +13,7 @@ sh3:
|
||||||
|
! Instructions introduced into sh3
|
||||||
|
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -128,8 +128,8 @@ sh3:
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh3e.s b/gas/testsuite/gas/sh/arch/sh3e.s
|
||||||
|
index f5c8ab9..215e5ec 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh3e.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh3e.s
|
||||||
|
@@ -12,7 +12,7 @@
|
||||||
|
sh3e:
|
||||||
|
! Instructions introduced into sh3e
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -132,8 +132,8 @@ sh3e:
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh4-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||||
|
index 32b58f9..1fef035 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||||
|
@@ -12,7 +12,7 @@
|
||||||
|
sh4_nofpu:
|
||||||
|
! Instructions introduced into sh4-nofpu
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -136,8 +136,8 @@ sh4_nofpu:
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||||
|
index 61f0bc6..65d11c5 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||||
|
@@ -24,7 +24,7 @@ sh4_nommu_nofpu:
|
||||||
|
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||||
|
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -139,8 +139,8 @@ sh4_nommu_nofpu:
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh4.s b/gas/testsuite/gas/sh/arch/sh4.s
|
||||||
|
index af135ce..dc199cb 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh4.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh4.s
|
||||||
|
@@ -17,7 +17,7 @@ sh4:
|
||||||
|
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||||
|
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -145,8 +145,8 @@ sh4:
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||||
|
index 9522bb6..7581f47 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||||
|
@@ -19,7 +19,7 @@ sh4a_nofpu:
|
||||||
|
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||||
|
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -143,8 +143,8 @@ sh4a_nofpu:
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh4a.s b/gas/testsuite/gas/sh/arch/sh4a.s
|
||||||
|
index 950ed2d..55e9611 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh4a.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh4a.s
|
||||||
|
@@ -13,7 +13,7 @@ sh4a:
|
||||||
|
! Instructions introduced into sh4a
|
||||||
|
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||||
|
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -147,8 +147,8 @@ sh4a:
|
||||||
|
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||||
|
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||||
|
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/gas/testsuite/gas/sh/arch/sh4al-dsp.s b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||||
|
index 6caaf2c..fde6c1e 100644
|
||||||
|
--- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||||
|
+++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||||
|
@@ -48,7 +48,7 @@ sh4al_dsp:
|
||||||
|
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||||
|
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||||
|
|
||||||
|
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||||
|
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||||
|
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||||
|
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||||
|
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||||
|
@@ -202,8 +202,8 @@ sh4al_dsp:
|
||||||
|
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||||
|
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||||
|
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||||
|
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||||
|
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||||
|
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||||
|
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||||
|
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||||
|
diff --git a/include/elf/sh.h b/include/elf/sh.h
|
||||||
|
index a54158f..109d90f 100644
|
||||||
|
--- a/include/elf/sh.h
|
||||||
|
+++ b/include/elf/sh.h
|
||||||
|
@@ -35,6 +35,7 @@
|
||||||
|
#define EF_SH2E 11
|
||||||
|
#define EF_SH4A 12
|
||||||
|
#define EF_SH2A 13
|
||||||
|
+#define EF_SHJ2 14
|
||||||
|
|
||||||
|
#define EF_SH4_NOFPU 16
|
||||||
|
#define EF_SH4A_NOFPU 17
|
||||||
|
@@ -46,6 +47,7 @@
|
||||||
|
#define EF_SH2A_SH3_NOFPU 22
|
||||||
|
#define EF_SH2A_SH4 23
|
||||||
|
#define EF_SH2A_SH3E 24
|
||||||
|
+#define EF_SH2A_SH3_SHJ2 25
|
||||||
|
|
||||||
|
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||||
|
#define EF_SH5 10
|
||||||
|
@@ -68,7 +70,8 @@
|
||||||
|
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||||
|
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||||
|
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||||
|
-/* 14, 15 */ 0, 0, \
|
||||||
|
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||||
|
+/* 15 */ 0, \
|
||||||
|
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||||
|
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||||
|
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||||
|
@@ -77,7 +80,8 @@
|
||||||
|
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||||
|
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||||
|
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||||
|
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||||
|
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||||
|
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||||
|
|
||||||
|
/* Convert arch_sh* into EF_SH*. */
|
||||||
|
int sh_find_elf_flags (unsigned int arch_set);
|
||||||
|
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
|
||||||
|
index d4e1a6d..181e21a 100644
|
||||||
|
--- a/opcodes/sh-dis.c
|
||||||
|
+++ b/opcodes/sh-dis.c
|
||||||
|
@@ -868,6 +868,9 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
|
||||||
|
case XMTRX_M4:
|
||||||
|
fprintf_fn (stream, "xmtrx");
|
||||||
break;
|
break;
|
||||||
+ case A_IND_0:
|
+ case A_IND_0:
|
||||||
+ fprintf_fn (stream, "@r0");
|
+ fprintf_fn (stream, "@r0");
|
||||||
+ break;
|
+ break;
|
||||||
case A_IND_N:
|
default:
|
||||||
case AS_IND_N:
|
abort ();
|
||||||
fprintf_fn (stream, "@r%d", rn);
|
}
|
||||||
--- binutils-2.25.1.orig/opcodes/sh-opc.h
|
diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
|
||||||
+++ binutils-2.25.1/opcodes/sh-opc.h
|
index 5863aa9..19c5a61 100644
|
||||||
@@ -112,6 +112,7 @@
|
--- a/opcodes/sh-opc.h
|
||||||
A_IMM,
|
+++ b/opcodes/sh-opc.h
|
||||||
A_INC_M,
|
@@ -187,7 +187,8 @@ typedef enum
|
||||||
A_INC_N,
|
FPUL_N,
|
||||||
+ A_IND_0,
|
FPUL_M,
|
||||||
A_IND_M,
|
FPSCR_N,
|
||||||
A_IND_N,
|
- FPSCR_M
|
||||||
A_IND_R0_REG_M,
|
+ FPSCR_M,
|
||||||
@@ -410,6 +411,8 @@
|
+ A_IND_0
|
||||||
/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
|
}
|
||||||
|
sh_arg_type;
|
||||||
|
|
||||||
/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
|
@@ -214,9 +215,11 @@ sh_dsp_reg_nums;
|
||||||
+
|
#define arch_sh4_base (1 << 5)
|
||||||
+/* 0010nnnnmmmm0011 cas.l <REG_M>,<REG_N>,@R0*/{"cas.l",{A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_sh2_up},
|
#define arch_sh4a_base (1 << 6)
|
||||||
|
#define arch_sh2a_base (1 << 7)
|
||||||
|
-#define arch_sh_base_mask MASK (0, 7)
|
||||||
|
+#define arch_shj2_base (1 << 8)
|
||||||
|
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||||
|
+#define arch_sh_base_mask MASK (0, 9)
|
||||||
|
|
||||||
/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
|
-/* Bits 8 ... 24 are currently free. */
|
||||||
|
+/* Bits 10 ... 24 are currently free. */
|
||||||
|
|
||||||
|
/* This is an annotation on instruction types, but we
|
||||||
|
abuse the arch field in instructions to denote it. */
|
||||||
|
@@ -254,6 +257,8 @@ sh_dsp_reg_nums;
|
||||||
|
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||||
|
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||||
|
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||||
|
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||||
|
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||||
|
|
||||||
|
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||||
|
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||||
|
@@ -319,7 +324,8 @@ SH4AL-dsp SH4A
|
||||||
|
#define arch_sh2_up (arch_sh2 \
|
||||||
|
| arch_sh2e_up \
|
||||||
|
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||||
|
- | arch_sh_dsp_up)
|
||||||
|
+ | arch_sh_dsp_up \
|
||||||
|
+ | arch_shj2_up)
|
||||||
|
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||||
|
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||||
|
| arch_sh2a_or_sh3e_up \
|
||||||
|
@@ -345,6 +351,12 @@ SH4AL-dsp SH4A
|
||||||
|
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||||
|
| arch_sh4a_up \
|
||||||
|
| arch_sh4al_dsp_up)
|
||||||
|
+#define arch_shj2_up ( arch_shj2)
|
||||||
|
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||||
|
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||||
|
+ | arch_sh2a_or_sh3e_up \
|
||||||
|
+ | arch_sh3_nommu_up \
|
||||||
|
+ | arch_shj2_up)
|
||||||
|
|
||||||
|
/* Right branches. */
|
||||||
|
#define arch_sh2e_up (arch_sh2e \
|
||||||
|
@@ -713,9 +725,9 @@ const sh_opcode_info sh_table[] =
|
||||||
|
|
||||||
|
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||||
|
|
||||||
|
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||||
|
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||||
|
|
||||||
|
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||||
|
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||||
|
|
||||||
|
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||||
|
|
||||||
|
@@ -1193,7 +1205,7 @@ const sh_opcode_info sh_table[] =
|
||||||
|
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||||
|
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||||
|
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||||
|
-
|
||||||
|
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||||
|
{ 0, {0}, {0}, 0 }
|
||||||
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,49 @@
|
||||||
--- gcc-5.2.0.orig/gcc/config.gcc
|
diff --git a/gcc/config.gcc b/gcc/config.gcc
|
||||||
+++ gcc-5.2.0/gcc/config.gcc
|
index 0f2dc32..a3d0d45 100644
|
||||||
@@ -2668,7 +2671,7 @@
|
--- a/gcc/config.gcc
|
||||||
|
+++ b/gcc/config.gcc
|
||||||
|
@@ -467,7 +467,7 @@ s390*-*-*)
|
||||||
|
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
|
||||||
|
;;
|
||||||
|
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
|
||||||
|
-sh[123456789lbe]*-*-* | sh-*-*)
|
||||||
|
+sh[123456789lbej]*-*-* | sh-*-*)
|
||||||
|
cpu_type=sh
|
||||||
|
extra_options="${extra_options} fused-madd.opt"
|
||||||
|
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
|
||||||
|
@@ -2601,19 +2601,19 @@ s390x-ibm-tpf*)
|
||||||
|
extra_options="${extra_options} s390/tpf.opt"
|
||||||
|
tmake_file="${tmake_file} s390/t-s390"
|
||||||
|
;;
|
||||||
|
-sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||||
|
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
|
||||||
|
+sh-*-elf* | sh[12346lj]*-*-elf* | \
|
||||||
|
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
|
||||||
|
sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
|
||||||
|
sh64-*-netbsd* | sh64l*-*-netbsd*)
|
||||||
|
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
|
||||||
|
if test x${with_endian} = x; then
|
||||||
|
case ${target} in
|
||||||
|
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
|
||||||
|
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
|
||||||
|
shbe-*-* | sheb-*-*) with_endian=big,little ;;
|
||||||
|
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
|
||||||
|
shl* | sh64l* | sh*-*-linux* | \
|
||||||
|
sh5l* | sh-superh-elf) with_endian=little,big ;;
|
||||||
|
- sh[1234]*-*-*) with_endian=big ;;
|
||||||
|
+ sh[j1234]*-*-*) with_endian=big ;;
|
||||||
|
*) with_endian=big,little ;;
|
||||||
|
esac
|
||||||
|
fi
|
||||||
|
@@ -2703,6 +2703,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||||
|
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
|
||||||
|
sh2a*) sh_cpu_target=sh2a ;;
|
||||||
|
sh2e*) sh_cpu_target=sh2e ;;
|
||||||
|
+ shj2*) sh_cpu_target=shj2;;
|
||||||
|
sh2*) sh_cpu_target=sh2 ;;
|
||||||
|
*) sh_cpu_target=sh1 ;;
|
||||||
|
esac
|
||||||
|
@@ -2727,7 +2728,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||||
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
|
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
|
||||||
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
|
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
|
||||||
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
|
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
|
||||||
|
|
@ -9,18 +52,37 @@
|
||||||
"") sh_cpu_default=${sh_cpu_target} ;;
|
"") sh_cpu_default=${sh_cpu_target} ;;
|
||||||
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
|
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
|
||||||
esac
|
esac
|
||||||
@@ -2687,9 +2690,9 @@
|
@@ -2738,9 +2739,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||||
|
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
|
||||||
|
sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
|
||||||
|
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
|
||||||
|
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
|
||||||
|
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
|
||||||
|
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
|
||||||
|
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
|
||||||
|
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
|
||||||
|
esac
|
||||||
|
if test x$with_fp = xno; then
|
||||||
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
|
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
|
||||||
|
@@ -2758,7 +2759,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||||
|
m2a | m2a-single | m2a-single-only | m2a-nofpu | \
|
||||||
|
m5-64media | m5-64media-nofpu | \
|
||||||
|
m5-32media | m5-32media-nofpu | \
|
||||||
|
- m5-compact | m5-compact-nofpu)
|
||||||
|
+ m5-compact | m5-compact-nofpu | \
|
||||||
|
+ mj2)
|
||||||
|
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
|
||||||
|
# It is passed to MULTIILIB_OPTIONS verbatim.
|
||||||
|
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
|
||||||
|
@@ -2775,7 +2777,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||||
|
done
|
||||||
|
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
|
||||||
|
if test x${enable_incomplete_targets} = xyes ; then
|
||||||
|
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
|
||||||
|
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1"
|
||||||
fi
|
fi
|
||||||
fi
|
tm_file="$tm_file ./sysroot-suffix.h"
|
||||||
- target_cpu_default=SELECT_`echo ${sh_cpu_default}|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`
|
tmake_file="$tmake_file t-sysroot-suffix"
|
||||||
+ target_cpu_default=SELECT_`echo ${sh_cpu_default}|sed 's/^shj/j/'|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`
|
|
||||||
tm_defines=${tm_defines}' SH_MULTILIB_CPU_DEFAULT=\"'`echo $sh_cpu_default|sed s/sh/m/`'\"'
|
|
||||||
- tm_defines="$tm_defines SUPPORT_`echo $sh_cpu_default | sed 's/^m/sh/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1"
|
|
||||||
+ tm_defines="$tm_defines SUPPORT_`echo $sh_cpu_default | sed -e 's/^m/sh/' -e 's/^shj/j/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1"
|
|
||||||
sh_multilibs=`echo $sh_multilibs | sed -e 's/,/ /g' -e 's/^[Ss][Hh]/m/' -e 's/ [Ss][Hh]/ m/g' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz-`
|
|
||||||
for sh_multilib in ${sh_multilibs}; do
|
|
||||||
case ${sh_multilib} in
|
|
||||||
@@ -4106,6 +4109,8 @@
|
@@ -4106,6 +4109,8 @@
|
||||||
;;
|
;;
|
||||||
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
|
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
|
||||||
|
|
@ -30,62 +92,258 @@
|
||||||
*)
|
*)
|
||||||
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
|
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
|
||||||
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
|
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
|
||||||
--- gcc-5.2.0.orig/gcc/config/sh/sh.h
|
@@ -4456,7 +4458,7 @@ case ${target} in
|
||||||
+++ gcc-5.2.0/gcc/config/sh/sh.h
|
tmake_file="rs6000/t-rs6000 ${tmake_file}"
|
||||||
@@ -139,6 +139,7 @@
|
;;
|
||||||
#define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
|
|
||||||
| MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
|
- sh[123456ble]*-*-* | sh-*-*)
|
||||||
| MASK_SH2 | MASK_SH1)
|
+ sh[123456blej]*-*-* | sh-*-*)
|
||||||
+#define SELECT_J2 (MASK_SH2 | MASK_J2 | SELECT_SH1)
|
c_target_objs="${c_target_objs} sh-c.o"
|
||||||
#define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
|
cxx_target_objs="${cxx_target_objs} sh-c.o"
|
||||||
#define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
|
;;
|
||||||
#define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
|
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
|
||||||
@@ -162,6 +163,9 @@
|
index b08120d..63b77fa 100644
|
||||||
#define SUPPORT_SH2 1
|
--- a/gcc/config/sh/sh-protos.h
|
||||||
|
+++ b/gcc/config/sh/sh-protos.h
|
||||||
|
@@ -45,6 +45,7 @@ struct sh_atomic_model
|
||||||
|
hard_llcs,
|
||||||
|
soft_tcb,
|
||||||
|
soft_imask,
|
||||||
|
+ hard_cas,
|
||||||
|
|
||||||
|
num_models
|
||||||
|
};
|
||||||
|
@@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
|
||||||
|
#define TARGET_ATOMIC_SOFT_IMASK \
|
||||||
|
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
|
||||||
|
|
||||||
|
+#define TARGET_ATOMIC_HARD_CAS \
|
||||||
|
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
|
||||||
|
+
|
||||||
|
#ifdef RTX_CODE
|
||||||
|
extern rtx sh_fsca_sf2int (void);
|
||||||
|
extern rtx sh_fsca_int2sf (void);
|
||||||
|
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
|
||||||
|
index 0b18ce5..bdf96e2 100644
|
||||||
|
--- a/gcc/config/sh/sh.c
|
||||||
|
+++ b/gcc/config/sh/sh.c
|
||||||
|
@@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||||
|
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
|
||||||
|
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
|
||||||
|
model_names[sh_atomic_model::soft_imask] = "soft-imask";
|
||||||
|
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
|
||||||
|
|
||||||
|
const char* model_cdef_names[sh_atomic_model::num_models];
|
||||||
|
model_cdef_names[sh_atomic_model::none] = "NONE";
|
||||||
|
@@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||||
|
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
|
||||||
|
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
|
||||||
|
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
|
||||||
|
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
|
||||||
|
|
||||||
|
sh_atomic_model ret;
|
||||||
|
ret.type = sh_atomic_model::none;
|
||||||
|
@@ -780,6 +782,9 @@ got_mode_name:;
|
||||||
|
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
|
||||||
|
err_ret ("cannot use atomic model %s in user mode", ret.name);
|
||||||
|
|
||||||
|
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
|
||||||
|
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
|
||||||
|
+
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
#undef err_ret
|
||||||
|
@@ -845,6 +850,8 @@ sh_option_override (void)
|
||||||
|
sh_cpu = PROCESSOR_SH2E;
|
||||||
|
if (TARGET_SH2A)
|
||||||
|
sh_cpu = PROCESSOR_SH2A;
|
||||||
|
+ if (TARGET_SHJ2)
|
||||||
|
+ sh_cpu = PROCESSOR_SHJ2;
|
||||||
|
if (TARGET_SH3)
|
||||||
|
sh_cpu = PROCESSOR_SH3;
|
||||||
|
if (TARGET_SH3E)
|
||||||
|
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
|
||||||
|
index 7187c23..9d0d1d0 100644
|
||||||
|
--- a/gcc/config/sh/sh.h
|
||||||
|
+++ b/gcc/config/sh/sh.h
|
||||||
|
@@ -106,6 +106,7 @@ extern int code_for_indirect_jump_scratch;
|
||||||
|
#define SUPPORT_SH4_SINGLE 1
|
||||||
|
#define SUPPORT_SH2A 1
|
||||||
|
#define SUPPORT_SH2A_SINGLE 1
|
||||||
|
+#define SUPPORT_SHJ2 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#define TARGET_DIVIDE_INV \
|
||||||
|
@@ -157,6 +158,7 @@ extern int code_for_indirect_jump_scratch;
|
||||||
|
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
|
||||||
|
#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
|
||||||
|
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
|
||||||
|
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
|
||||||
|
|
||||||
|
#if SUPPORT_SH1
|
||||||
|
#define SUPPORT_SH2 1
|
||||||
|
@@ -164,6 +166,7 @@ extern int code_for_indirect_jump_scratch;
|
||||||
#if SUPPORT_SH2
|
#if SUPPORT_SH2
|
||||||
+#define SUPPORT_J2 1
|
|
||||||
+#endif
|
|
||||||
+#ifdef SUPPORT_J2
|
|
||||||
#define SUPPORT_SH3 1
|
#define SUPPORT_SH3 1
|
||||||
#define SUPPORT_SH2A_NOFPU 1
|
#define SUPPORT_SH2A_NOFPU 1
|
||||||
|
+#define SUPPORT_SHJ2 1
|
||||||
#endif
|
#endif
|
||||||
@@ -211,7 +215,7 @@
|
#if SUPPORT_SH3
|
||||||
|
#define SUPPORT_SH4_NOFPU 1
|
||||||
|
@@ -211,7 +214,7 @@ extern int code_for_indirect_jump_scratch;
|
||||||
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
|
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
|
||||||
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
|
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
|
||||||
| MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
|
| MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
|
||||||
- | MASK_FPU_SINGLE_ONLY)
|
- | MASK_FPU_SINGLE_ONLY)
|
||||||
+ | MASK_FPU_SINGLE_ONLY | MASK_J2)
|
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
|
||||||
|
|
||||||
/* This defaults us to big-endian. */
|
/* This defaults us to big-endian. */
|
||||||
#ifndef TARGET_ENDIAN_DEFAULT
|
#ifndef TARGET_ENDIAN_DEFAULT
|
||||||
@@ -271,6 +275,7 @@
|
@@ -289,8 +292,8 @@ extern int code_for_indirect_jump_scratch;
|
||||||
%(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
|
%{m5-compact*:--isa=SHcompact} \
|
||||||
%{m1:--isa=sh} \
|
%{m5-32media*:--isa=SHmedia --abi=32} \
|
||||||
%{m2:--isa=sh2} \
|
%{m5-64media*:--isa=SHmedia --abi=64} \
|
||||||
+%{mj2:--isa=any} \
|
-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
|
||||||
%{m2e:--isa=sh2e} \
|
-
|
||||||
%{m3:--isa=sh3} \
|
+%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \
|
||||||
%{m3e:--isa=sh3e} \
|
+%{mj2:-isa=j2}"
|
||||||
@@ -1834,7 +1839,7 @@
|
#define ASM_SPEC SH_ASM_SPEC
|
||||||
|
|
||||||
|
#ifndef SUBTARGET_ASM_ENDIAN_SPEC
|
||||||
|
@@ -1853,7 +1856,7 @@ struct sh_args {
|
||||||
|
|
||||||
/* Nonzero if the target supports dynamic shift instructions
|
/* Nonzero if the target supports dynamic shift instructions
|
||||||
like shad and shld. */
|
like shad and shld. */
|
||||||
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
|
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
|
||||||
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_J2)
|
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
|
||||||
|
|
||||||
/* The cost of using the dynamic shift insns (shad, shld) are the same
|
/* The cost of using the dynamic shift insns (shad, shld) are the same
|
||||||
if they are available. If they are not available a library function will
|
if they are available. If they are not available a library function will
|
||||||
--- gcc-5.2.0.orig/gcc/config/sh/sh.opt
|
@@ -2185,6 +2188,7 @@ enum processor_type {
|
||||||
+++ gcc-5.2.0/gcc/config/sh/sh.opt
|
PROCESSOR_SH2,
|
||||||
@@ -71,6 +71,10 @@
|
PROCESSOR_SH2E,
|
||||||
|
PROCESSOR_SH2A,
|
||||||
|
+ PROCESSOR_SHJ2,
|
||||||
|
PROCESSOR_SH3,
|
||||||
|
PROCESSOR_SH3E,
|
||||||
|
PROCESSOR_SH4,
|
||||||
|
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
|
||||||
|
index 1026c73..bac47ed 100644
|
||||||
|
--- a/gcc/config/sh/sh.opt
|
||||||
|
+++ b/gcc/config/sh/sh.opt
|
||||||
|
@@ -71,6 +71,10 @@ m2e
|
||||||
Target RejectNegative Condition(SUPPORT_SH2E)
|
Target RejectNegative Condition(SUPPORT_SH2E)
|
||||||
Generate SH2e code
|
Generate SH2e code.
|
||||||
|
|
||||||
+mj2
|
+mj2
|
||||||
+Target RejectNegative Mask(J2) Condition(SUPPORT_J2)
|
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
|
||||||
+Generate J2 code
|
+Generate J2 code.
|
||||||
+
|
+
|
||||||
m3
|
m3
|
||||||
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
|
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
|
||||||
Generate SH3 code
|
Generate SH3 code.
|
||||||
|
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
|
||||||
|
index 6f1337b..cff57b8 100644
|
||||||
|
--- a/gcc/config/sh/sync.md
|
||||||
|
+++ b/gcc/config/sh/sync.md
|
||||||
|
@@ -240,6 +240,9 @@
|
||||||
|
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|
||||||
|
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
|
||||||
|
exp_val, new_val);
|
||||||
|
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
|
||||||
|
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
|
||||||
|
+ exp_val, new_val);
|
||||||
|
else if (TARGET_ATOMIC_SOFT_GUSA)
|
||||||
|
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
|
||||||
|
exp_val, new_val);
|
||||||
|
@@ -306,6 +309,57 @@
|
||||||
|
}
|
||||||
|
[(set_attr "length" "14")])
|
||||||
|
|
||||||
|
+(define_expand "atomic_compare_and_swapsi_cas"
|
||||||
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
||||||
|
+ (unspec_volatile:SI
|
||||||
|
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||||
|
+ (match_operand:SI 2 "register_operand" "r")
|
||||||
|
+ (match_operand:SI 3 "register_operand" "r")]
|
||||||
|
+ UNSPECV_CMPXCHG_1))]
|
||||||
|
+ "TARGET_ATOMIC_HARD_CAS"
|
||||||
|
+{
|
||||||
|
+ rtx mem = gen_rtx_REG (SImode, 0);
|
||||||
|
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
|
||||||
|
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
|
||||||
|
+ DONE;
|
||||||
|
+})
|
||||||
|
+
|
||||||
|
+(define_insn "shj2_cas"
|
||||||
|
+ [(set (match_operand:SI 0 "register_operand" "=&r")
|
||||||
|
+ (unspec_volatile:SI
|
||||||
|
+ [(match_operand:SI 1 "register_operand" "=r")
|
||||||
|
+ (match_operand:SI 2 "register_operand" "r")
|
||||||
|
+ (match_operand:SI 3 "register_operand" "0")]
|
||||||
|
+ UNSPECV_CMPXCHG_1))
|
||||||
|
+ (set (reg:SI T_REG)
|
||||||
|
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
|
||||||
|
+ "TARGET_ATOMIC_HARD_CAS"
|
||||||
|
+ "cas.l %2,%0,@%1"
|
||||||
|
+ [(set_attr "length" "2")]
|
||||||
|
+)
|
||||||
|
+
|
||||||
|
+(define_expand "atomic_compare_and_swapqi_cas"
|
||||||
|
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||||
|
+ (unspec_volatile:SI
|
||||||
|
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||||
|
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||||
|
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||||
|
+ UNSPECV_CMPXCHG_1))]
|
||||||
|
+ "TARGET_ATOMIC_HARD_CAS"
|
||||||
|
+{FAIL;}
|
||||||
|
+)
|
||||||
|
+
|
||||||
|
+(define_expand "atomic_compare_and_swaphi_cas"
|
||||||
|
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||||
|
+ (unspec_volatile:SI
|
||||||
|
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||||
|
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||||
|
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||||
|
+ UNSPECV_CMPXCHG_1))]
|
||||||
|
+ "TARGET_ATOMIC_HARD_CAS"
|
||||||
|
+{FAIL;}
|
||||||
|
+)
|
||||||
|
+
|
||||||
|
;; The QIHImode llcs patterns modify the address register of the memory
|
||||||
|
;; operand. In order to express that, we have to open code the memory
|
||||||
|
;; operand. Initially the insn is expanded like every other atomic insn
|
||||||
|
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
|
||||||
|
index 348cc0b..8e6bdaf 100644
|
||||||
|
--- a/gcc/config/sh/t-sh
|
||||||
|
+++ b/gcc/config/sh/t-sh
|
||||||
|
@@ -52,7 +52,7 @@ MULTILIB_MATCHES = $(shell \
|
||||||
|
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
|
||||||
|
m4,m4-100,m4-200,m4-300,m4a \
|
||||||
|
m5-32media,m5-compact,m5-32media \
|
||||||
|
- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
|
||||||
|
+ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \
|
||||||
|
subst= ; \
|
||||||
|
for lib in `echo $$abi|tr , ' '` ; do \
|
||||||
|
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
|
||||||
|
@@ -65,9 +65,9 @@ MULTILIB_MATCHES = $(shell \
|
||||||
|
|
||||||
|
# SH1 and SH2A support big endian only.
|
||||||
|
ifeq ($(DEFAULT_ENDIAN),ml)
|
||||||
|
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||||
|
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||||
|
else
|
||||||
|
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||||
|
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||||
|
endif
|
||||||
|
|
||||||
|
MULTILIB_OSDIRNAMES = \
|
||||||
|
@@ -96,6 +96,7 @@ MULTILIB_OSDIRNAMES = \
|
||||||
|
m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
|
||||||
|
m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
|
||||||
|
m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
|
||||||
|
+ mj2=!j2
|
||||||
|
|
||||||
|
$(out_object_file): gt-sh.h
|
||||||
|
gt-sh.h : s-gtype ; @true
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue