mirror of
https://github.com/richfelker/musl-cross-make.git
synced 2025-04-18 15:04:59 +02:00
Feat: mingw support
This commit is contained in:
zijiren233
parent
3278ec1f9c
commit
a07b9afb92
1
.gitignore
vendored
1
.gitignore
vendored
@ -11,3 +11,4 @@
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/linux-*/
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/isl-*/
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/build/
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/mingw-*/
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30
Makefile
30
Makefile
@ -2,13 +2,15 @@
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SOURCES = sources
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CONFIG_SUB_REV = 3d5db9ebe860
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BINUTILS_VER = 2.33.1
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GCC_VER = 9.4.0
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MUSL_VER = 1.2.3
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GMP_VER = 6.1.2
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MPC_VER = 1.1.0
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MPFR_VER = 4.0.2
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LINUX_VER = headers-4.19.88-1
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GCC_VER = 11.4.0
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MUSL_VER = 1.2.4
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BINUTILS_VER = 2.41
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GMP_VER = 6.3.0
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MPC_VER = 1.3.1
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MPFR_VER = 4.2.1
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ISL_VER =
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LINUX_VER =
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MINGW_VER = v11.0.1
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GNU_SITE = https://ftp.gnu.org/gnu
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GCC_SITE = $(GNU_SITE)/gcc
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@ -28,6 +30,8 @@ MUSL_REPO = git://git.musl-libc.org/musl
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LINUX_SITE = https://cdn.kernel.org/pub/linux/kernel
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LINUX_HEADERS_SITE = https://ftp.barfooze.de/pub/sabotage/tarballs/
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MINGW_SITE = https://sourceforge.net/projects/mingw-w64/files/mingw-w64/mingw-w64-release/
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DL_CMD = curl -sLo
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SHA1_CMD = sha1sum -c
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@ -41,17 +45,19 @@ REL_TOP = ../../..
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-include config.mak
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SRC_DIRS = gcc-$(GCC_VER) binutils-$(BINUTILS_VER) musl-$(MUSL_VER) \
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SRC_DIRS = gcc-$(GCC_VER) binutils-$(BINUTILS_VER) \
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$(if $(MUSL_VER),musl-$(MUSL_VER)) \
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$(if $(GMP_VER),gmp-$(GMP_VER)) \
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$(if $(MPC_VER),mpc-$(MPC_VER)) \
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$(if $(MPFR_VER),mpfr-$(MPFR_VER)) \
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$(if $(ISL_VER),isl-$(ISL_VER)) \
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$(if $(LINUX_VER),linux-$(LINUX_VER))
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$(if $(LINUX_VER),linux-$(LINUX_VER)) \
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$(if $(MINGW_VER),mingw-w64-$(MINGW_VER))
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all:
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clean:
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rm -rf gcc-* binutils-* musl-* gmp-* mpc-* mpfr-* isl-* build build-* linux-*
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rm -rf gcc-* binutils-* musl-* gmp-* mpc-* mpfr-* isl-* build build-* linux-* mingw-w64-*
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distclean: clean
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rm -rf sources
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@ -83,6 +89,7 @@ $(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-4*)): SITE = $(LIN
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$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-3*)): SITE = $(LINUX_SITE)/v3.x
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$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-2.6*)): SITE = $(LINUX_SITE)/v2.6
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$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-headers-*)): SITE = $(LINUX_HEADERS_SITE)
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$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/mingw-w64*)): SITE = $(MINGW_SITE)
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$(SOURCES):
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mkdir -p $@
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@ -183,14 +190,15 @@ $(BUILD_DIR)/config.mak: | $(BUILD_DIR)
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printf >$@ '%s\n' \
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"TARGET = $(TARGET)" \
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"HOST = $(HOST)" \
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"MUSL_SRCDIR = $(REL_TOP)/musl-$(MUSL_VER)" \
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"GCC_SRCDIR = $(REL_TOP)/gcc-$(GCC_VER)" \
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"BINUTILS_SRCDIR = $(REL_TOP)/binutils-$(BINUTILS_VER)" \
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$(if $(MUSL_VER),"MUSL_SRCDIR = $(REL_TOP)/musl-$(MUSL_VER)") \
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$(if $(GMP_VER),"GMP_SRCDIR = $(REL_TOP)/gmp-$(GMP_VER)") \
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$(if $(MPC_VER),"MPC_SRCDIR = $(REL_TOP)/mpc-$(MPC_VER)") \
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$(if $(MPFR_VER),"MPFR_SRCDIR = $(REL_TOP)/mpfr-$(MPFR_VER)") \
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$(if $(ISL_VER),"ISL_SRCDIR = $(REL_TOP)/isl-$(ISL_VER)") \
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$(if $(LINUX_VER),"LINUX_SRCDIR = $(REL_TOP)/linux-$(LINUX_VER)") \
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$(if $(MINGW_VER),"MINGW_SRCDIR = $(REL_TOP)/mingw-w64-$(MINGW_VER)") \
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"-include $(REL_TOP)/config.mak"
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all: | $(SRC_DIRS) $(BUILD_DIR) $(BUILD_DIR)/Makefile $(BUILD_DIR)/config.mak
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@ -80,6 +80,14 @@
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# GCC_CONFIG += --enable-languages=c,c++
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# recommend: disable building lib32 crt when building 64-bit compiler
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# MINGW_CRT_CONFIG += --disable-lib32 --enable-lib64 --disable-libarm32
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# if you'd like your toolchain to target the Universal CRT instead of MSVCRT,
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# uncomment the following lines
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# MINGW_CRT_CONFIG += --with-default-msvcrt=ucrt
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# MINGW_HEADERS_CONFIG += --with-default-msvcrt=ucrt
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# Binutils 2.32 and newer (default in mcm since mid-2019) default to emit
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# compressed debug info sections, which are a relatively new feature that
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# breaks older tooling, such as using so built libraries/executables with
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1
hashes/config.sub.0b5188819ba6.sha1
Normal file
1
hashes/config.sub.0b5188819ba6.sha1
Normal file
@ -0,0 +1 @@
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27caf5257eba3c90092f70946315206f8bdffa27 config.sub
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1
hashes/config.sub.59e2ce0e6b46.sha1
Normal file
1
hashes/config.sub.59e2ce0e6b46.sha1
Normal file
@ -0,0 +1 @@
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acb5dfe011a26adbf9e43e0279166dd412f2a830 config.sub
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1
hashes/isl-0.22.1.tar.bz2.sha1
Normal file
1
hashes/isl-0.22.1.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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e2f10d5a071796bebc79c6df5d26258f42cf6333 isl-0.22.1.tar.bz2
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1
hashes/isl-0.23.tar.bz2.sha1
Normal file
1
hashes/isl-0.23.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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ed28663a94320ba368a60afedbad8005af8beaf3 isl-0.23.tar.bz2
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1
hashes/linux-5.15.2.tar.xz.sha1
Normal file
1
hashes/linux-5.15.2.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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a7515341d798794a1c1094e6f7e845d2caeae0a2 linux-5.15.2.tar.xz
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1
hashes/linux-5.2.11.tar.xz.sha1
Normal file
1
hashes/linux-5.2.11.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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98543f7b4335d987bfef88b00b6f8cb9e3c469ff linux-5.2.11.tar.xz
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1
hashes/linux-5.4.100.tar.xz.sha1
Normal file
1
hashes/linux-5.4.100.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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cc74a48c0227aa5fffa031e3a84a92bc62e032e4 linux-5.4.100.tar.xz
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1
hashes/linux-5.4.18.tar.xz.sha1
Normal file
1
hashes/linux-5.4.18.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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c8a307813ecbbbf579f8f3727b8f8284070ac9c5 linux-5.4.18.tar.xz
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1
hashes/linux-5.4.24.tar.xz.sha1
Normal file
1
hashes/linux-5.4.24.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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365074c9c7d412d3ef8265b3ab60f52ec0f45605 linux-5.4.24.tar.xz
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1
hashes/linux-5.4.35.tar.xz.sha1
Normal file
1
hashes/linux-5.4.35.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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a6e0f6303be334182b031a15fefc709fb18b20b8 linux-5.4.35.tar.xz
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1
hashes/linux-5.4.47.tar.xz.sha1
Normal file
1
hashes/linux-5.4.47.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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a259b0847c17991cfdd6ba5ee80317f4b59a873f linux-5.4.47.tar.xz
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1
hashes/linux-5.4.50.tar.xz.sha1
Normal file
1
hashes/linux-5.4.50.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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f8045fed27da1522487c092272b4b916f3efab75 linux-5.4.50.tar.xz
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1
hashes/linux-5.4.61.tar.xz.sha1
Normal file
1
hashes/linux-5.4.61.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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eded1303e8c011c3a8052f7f8649d3189373c684 linux-5.4.61.tar.xz
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1
hashes/linux-5.4.78.tar.xz.sha1
Normal file
1
hashes/linux-5.4.78.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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1121e30eda15903e9e6054c9c525a2525bfd1694 linux-5.4.78.tar.xz
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1
hashes/linux-5.4.8.tar.xz.sha1
Normal file
1
hashes/linux-5.4.8.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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c0e993361b2607ca3ab38d4d103a21e8485e190b linux-5.4.8.tar.xz
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1
hashes/linux-5.4.80.tar.xz.sha1
Normal file
1
hashes/linux-5.4.80.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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d4f95b7e2d9fd4826755dbb5d234ae424f5f7325 linux-5.4.80.tar.xz
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1
hashes/linux-5.4.89.tar.xz.sha1
Normal file
1
hashes/linux-5.4.89.tar.xz.sha1
Normal file
@ -0,0 +1 @@
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3d9a0da5bfb7559f8a5acc852effe995e8190e14 linux-5.4.89.tar.xz
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1
hashes/mingw-w64-v11.0.0.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v11.0.0.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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a6902ac07d4704d76bb3890713bb1c3d46e4dc89 mingw-w64-v11.0.0.tar.bz2
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1
hashes/mingw-w64-v11.0.1.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v11.0.1.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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ab23c9af10fb38388ac75145dd9ffed3c64d1eeb mingw-w64-v11.0.1.tar.bz2
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1
hashes/mingw-w64-v5.0.1.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v5.0.1.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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ea0e0b73982b8f5e296fa519353e49a94326fa5a mingw-w64-v5.0.1.tar.bz2
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1
hashes/mingw-w64-v5.0.2.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v5.0.2.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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bb5409f034abb7c021b3e1c14db433fd253cbb59 mingw-w64-v5.0.2.tar.bz2
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1
hashes/mingw-w64-v5.0.3.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v5.0.3.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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96278378b829695007ce6a527278cba19cb829f2 mingw-w64-v5.0.3.tar.bz2
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1
hashes/mingw-w64-v5.0.4.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v5.0.4.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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aa854d36acf575307b6b839f7ee12aa97f66af29 mingw-w64-v5.0.4.tar.bz2
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1
hashes/mingw-w64-v6.0.0.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v6.0.0.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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4cffb043060d88d6bf0f382e4d92019263670ca6 mingw-w64-v6.0.0.tar.bz2
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1
hashes/mingw-w64-v7.0.0.tar.bz2.sha1
Normal file
1
hashes/mingw-w64-v7.0.0.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
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25940043c4541e3e59608dead9b6f75b5596d606 mingw-w64-v7.0.0.tar.bz2
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@ -3,15 +3,22 @@ OUTPUT = $(CURDIR)/output
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BINUTILS_SRCDIR = BINUTILS_SRCDIR_not_set
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GCC_SRCDIR = GCC_SRCDIR_not_set
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MUSL_SRCDIR = MUSL_SRCDIR_not_set
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GCC_CONFIG_FOR_TARGET =
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COMMON_CONFIG =
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GCC_CONFIG =
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MINGW_CRT_CONFIG =
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MINGW_HEADERS_CONFIG =
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TOOLCHAIN_CONFIG =
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XGCC_DIR = ../obj_gcc/gcc
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XGCC = $(XGCC_DIR)/xgcc -B $(XGCC_DIR)
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XGCC_DIR = $(CURDIR)/obj_gcc/gcc
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XGCC = $(XGCC_DIR)/xgcc -B $(XGCC_DIR) -B $(CURDIR)/obj_sysroot/$(TARGET)/lib
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XCPP = $(XGCC_DIR)/cpp -B $(XGCC_DIR)
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XAR = $(CURDIR)/obj_binutils/binutils/ar
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XAS = $(CURDIR)/obj_binutils/gas/as-new
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XRANLIB = $(CURDIR)/obj_binutils/binutils/ranlib
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XRC = $(CURDIR)/obj_binutils/binutils/windres --preprocessor=$(XGCC_DIR)/xgcc --preprocessor-arg=-B --preprocessor-arg=$(XGCC_DIR) --preprocessor-arg=-I$(CURDIR)/obj_sysroot/$(TARGET)/include --preprocessor-arg=-E --preprocessor-arg=-xc-header --preprocessor-arg=-DRC_INVOKED -c 1252
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DLLTOOL = $(CURDIR)/obj_binutils/binutils/dlltool
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-include config.mak
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@ -19,6 +26,15 @@ ifeq ($(CPUS),)
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CPUS = $(shell if command -v nproc >/dev/null 2>&1; then nproc; else echo 1; fi)
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endif
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ifneq ($(findstring mingw,$(TARGET)),)
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MUSL_SRCDIR =
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LINUX_SRCDIR =
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endif
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ifneq ($(findstring musl,$(TARGET)),)
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MINGW_SRCDIR =
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# https://wiki.musl-libc.org/getting-started.html#Notes_on_ARM_Float_Mode
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ifeq ($(findstring armv5,$(TARGET)),armv5)
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GCC_CONFIG += --with-arch=armv5te --with-fpu=vfp
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@ -31,6 +47,7 @@ endif
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ifeq ($(findstring armv7,$(TARGET)),armv7)
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GCC_CONFIG += --with-arch=armv7-a --with-fpu=vfpv3
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endif
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endif
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ifneq ($(findstring fdpic,$(TARGET)),)
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GCC_CONFIG_FOR_TARGET += --enable-fdpic
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@ -109,9 +126,41 @@ FULL_GCC_CONFIG = --enable-languages=c,c++,fortran \
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--disable-decimal-float \
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$(OVERRIDE)
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# FULL_GCC_CONFIG = --enable-languages=c,c++,fortran \
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# $(GCC_CONFIG_FOR_TARGET) \
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# $(COMMON_CONFIG) $(GCC_CONFIG) $(TOOLCHAIN_CONFIG) \
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# --disable-bootstrap \
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# --disable-assembly \
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# --disable-werror \
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# --target=$(TARGET) --prefix= \
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# --libdir=/lib --disable-multilib \
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# --with-sysroot=$(SYSROOT) \
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# --enable-fully-dynamic-string \
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# --enable-libstdcxx-time=yes \
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# --enable-libstdcxx-filesystem-ts=yes \
|
||||
# --enable-cloog-backend=isl \
|
||||
# --disable-sjlj-exceptions \
|
||||
# --disable-multilib \
|
||||
# --with-dwarf2 \
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# --enable-deterministic-archives \
|
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# --enable-libstdcxx-time \
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# --enable-libquadmath --enable-libquadmath-support \
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# --disable-decimal-float \
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# $(OVERRIDE)
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|
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FULL_MUSL_CONFIG = $(MUSL_CONFIG) \
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--prefix= --host=$(TARGET)
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FULL_MINGW_HEADERS_CONFIG = $(MINGW_CONFIG) $(MINGW_HEADERS_CONFIG) \
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--prefix= --host=$(TARGET) --enable-sdk=all \
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--enable-idl --enable-secure-api --with-sysroot=$(SYSROOT)
|
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|
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FULL_MINGW_CRT_CONFIG = $(MINGW_CONFIG) $(MINGW_CRT_CONFIG) \
|
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--prefix= --host=$(TARGET) --with-sysroot=$(SYSROOT)
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|
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FULL_MINGW_PTHREADS_CONFIG = $(MINGW_CONFIG) \
|
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--prefix= --host=$(TARGET) --with-sysroot=$(SYSROOT)
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ifneq ($(NATIVE),)
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HOST:=$(TARGET)
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endif
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@ -139,10 +188,21 @@ FULL_GCC_CONFIG += --with-build-sysroot=$(CURDIR)/obj_sysroot \
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# end
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FULL_MUSL_CONFIG += CC="$(XGCC)" LIBCC="../obj_gcc/$(TARGET)/libgcc/libgcc.a"
|
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MUSL_VARS = AR=../obj_binutils/binutils/ar RANLIB=../obj_binutils/binutils/ranlib
|
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MINGW_VARS = AS="$(XAS)" AR="$(XAR)" CC="$(XGCC)" RANLIB="$(XRANLIB)"
|
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FULL_MINGW_PTHREADS_CONFIG += RC="$(XRC)" CC="$(XGCC)" CPP="$(XCPP)" CPPFLAGS="-I$(CURDIR)/obj_sysroot/$(TARGET)/include $(CPPFLAGS)" LDFLAGS="-L$(CURDIR)/obj_sysroot/$(TARGET)/lib $(LDFLAGS)" DLLTOOL=$(DLLTOOL)
|
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FULL_MINGW_CRT_CONFIG += CC="$(XGCC)" CPP="$(XCPP)" CPPFLAGS="-I$(CURDIR)/obj_sysroot/$(TARGET)/include $(CPPFLAGS)" DLLTOOL="$(DLLTOOL)" RC="$(XRC)"
|
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obj_mingw_headers/.lc_configured: | obj_binutils/.lc_built
|
||||
obj_mingw_crt/.lc_configured: | obj_sysroot/.lc_headers obj_gcc/gcc/.lc_built obj_binutils/.lc_built
|
||||
obj_mingw_pthreads/.lc_configured: | obj_sysroot/.lc_headers obj_gcc/gcc/.lc_built obj_binutils/.lc_built obj_sysroot/.lc_libs_crt
|
||||
obj_musl/.lc_configured: | obj_gcc/gcc/.lc_built
|
||||
obj_musl/.lc_built: | obj_gcc/$(TARGET)/libgcc/libgcc.a
|
||||
obj_gcc/gcc/.lc_built: | obj_sysroot/usr obj_sysroot/lib32 obj_sysroot/lib64 obj_sysroot/include
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
obj_gcc/.lc_built: | obj_sysroot/.lc_libs obj_sysroot/.lc_headers
|
||||
endif
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
obj_gcc/.lc_built: | obj_sysroot/.lc_libs_crt obj_sysroot/.lc_headers
|
||||
endif
|
||||
obj_gcc/.lc_configured: obj_binutils/.lc_built
|
||||
else
|
||||
SYSROOT = /
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||||
@ -161,12 +221,26 @@ install: all
|
||||
|
||||
else
|
||||
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
all: musl gcc binutils
|
||||
endif
|
||||
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
all: mingw gcc binutils
|
||||
endif
|
||||
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
install: install-musl install-gcc install-binutils
|
||||
endif
|
||||
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
install: install-mingw install-gcc install-binutils
|
||||
endif
|
||||
|
||||
musl: obj_musl/.lc_built
|
||||
|
||||
mingw: obj_mingw_headers/.lc_built obj_mingw_crt/.lc_built obj_mingw_pthreads/.lc_built
|
||||
|
||||
toolchain: gcc binutils
|
||||
|
||||
install-toolchain: install-gcc install-binutils
|
||||
@ -175,7 +249,7 @@ gcc: obj_gcc/.lc_built
|
||||
|
||||
binutils: obj_binutils/.lc_built
|
||||
|
||||
.PHONY: all musl toolchain install-musl install-toolchain clean
|
||||
.PHONY: all musl mingw toolchain install-musl install-mingw install-toolchain clean
|
||||
|
||||
src_binutils: | $(BINUTILS_SRCDIR)
|
||||
ln -sf $(BINUTILS_SRCDIR) $@
|
||||
@ -183,8 +257,15 @@ src_binutils: | $(BINUTILS_SRCDIR)
|
||||
src_gcc_base: | $(GCC_SRCDIR)
|
||||
ln -sf $(GCC_SRCDIR) $@
|
||||
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
src_musl: | $(MUSL_SRCDIR)
|
||||
ln -sf $(MUSL_SRCDIR) $@
|
||||
endif
|
||||
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
src_mingw: | $(MINGW_SRCDIR)
|
||||
ln -sf $(MINGW_SRCDIR) $@
|
||||
endif
|
||||
|
||||
ifneq ($(GMP_SRCDIR),)
|
||||
src_gcc: src_gmp
|
||||
@ -247,17 +328,54 @@ obj_gcc/.lc_configured: | obj_gcc src_gcc
|
||||
cd obj_gcc && ../src_gcc/configure $(FULL_GCC_CONFIG)
|
||||
touch $@
|
||||
|
||||
obj_gcc/gcc/.lc_built: | obj_gcc/.lc_configured
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_ARG)" all-gcc
|
||||
obj_gcc/.lc_gmp_built: | obj_gcc/.lc_configured
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_STATIC_ARG)" all-gmp
|
||||
touch $@
|
||||
|
||||
obj_gcc/.lc_mpfr_built: | obj_gcc/.lc_gmp_built
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_STATIC_ARG)" all-mpfr
|
||||
touch $@
|
||||
|
||||
obj_gcc/.lc_mpc_built: | obj_gcc/.lc_mpfr_built
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_STATIC_ARG)" all-mpc
|
||||
touch $@
|
||||
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
obj_gcc/gcc/.lc_built: | obj_gcc/.lc_mpc_built
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_ARG)" all-gcc
|
||||
touch $@
|
||||
endif
|
||||
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
obj_gcc/gcc/.lc_built: | obj_gcc/.lc_mpc_built obj_sysroot/.lc_headers
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_ARG)" all-gcc
|
||||
touch $@
|
||||
endif
|
||||
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
obj_musl/.lc_configured: | obj_musl src_musl
|
||||
cd obj_musl && ../src_musl/configure $(FULL_MUSL_CONFIG)
|
||||
touch $@
|
||||
endif
|
||||
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
obj_mingw/.lc_configured: | obj_mingw src_mingw obj_mingw_headers/.lc_configured obj_mingw_crt/.lc_configured
|
||||
touch $@
|
||||
endif
|
||||
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
obj_sysroot/.lc_headers: | obj_musl/.lc_configured obj_sysroot
|
||||
cd obj_musl && $(MAKE) -j$(CPUS) DESTDIR=$(CURDIR)/obj_sysroot install-headers
|
||||
touch $@
|
||||
endif
|
||||
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
obj_sysroot/.lc_headers: | obj_mingw_headers/.lc_configured obj_sysroot
|
||||
cd obj_mingw_headers && $(MAKE) -j$(CPUS) DESTDIR=$(CURDIR)/obj_sysroot/$(TARGET) install
|
||||
rm -f $(CURDIR)/obj_sysroot/mingw
|
||||
ln -s $(TARGET) $(CURDIR)/obj_sysroot/mingw
|
||||
touch $@
|
||||
endif
|
||||
|
||||
obj_gcc/$(TARGET)/libgcc/libgcc.a: | obj_sysroot/.lc_headers
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) enable_shared=no $(LIBTOOL_ARG)" all-target-libgcc
|
||||
@ -266,9 +384,16 @@ obj_musl/.lc_built: | obj_musl/.lc_configured
|
||||
cd obj_musl && $(MAKE) -j$(CPUS) $(MUSL_VARS)
|
||||
touch $@
|
||||
|
||||
ifneq ($(MUSL_SRCDIR),)
|
||||
obj_sysroot/.lc_libs: | obj_musl/.lc_built
|
||||
cd obj_musl && $(MAKE) -j$(CPUS) $(MUSL_VARS) DESTDIR=$(CURDIR)/obj_sysroot install
|
||||
touch $@
|
||||
endif
|
||||
|
||||
ifneq ($(MINGW_SRCDIR),)
|
||||
obj_sysroot/.lc_libs: | obj_sysroot/.lc_libs_pthreads obj_sysroot/.lc_libs_crt
|
||||
touch $@
|
||||
endif
|
||||
|
||||
obj_gcc/.lc_built: | obj_gcc/.lc_configured obj_gcc/gcc/.lc_built
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_ARG)"
|
||||
@ -284,6 +409,49 @@ install-gcc: | obj_gcc/.lc_built
|
||||
cd obj_gcc && $(MAKE) -j$(CPUS) MAKE="$(MAKE) $(LIBTOOL_ARG)" DESTDIR=$(DESTDIR)$(OUTPUT) install
|
||||
ln -sf $(TARGET)-gcc $(DESTDIR)$(OUTPUT)/bin/$(TARGET)-cc
|
||||
|
||||
obj_mingw_headers/.lc_configured: | obj_mingw_headers src_mingw
|
||||
cd obj_mingw_headers && ../src_mingw/mingw-w64-headers/configure $(FULL_MINGW_HEADERS_CONFIG)
|
||||
touch $@
|
||||
|
||||
obj_mingw_headers/.lc_built: | obj_mingw_headers/.lc_configured
|
||||
cd obj_mingw_headers && $(MAKE) -j$(CPUS) $(MINGW_VARS)
|
||||
touch $@
|
||||
|
||||
obj_mingw_crt/.lc_configured: | obj_sysroot/.lc_headers obj_binutils/.lc_built obj_gcc/gcc/.lc_built obj_mingw_crt src_mingw
|
||||
cd obj_mingw_crt && ../src_mingw/mingw-w64-crt/configure $(FULL_MINGW_CRT_CONFIG)
|
||||
touch $@
|
||||
|
||||
obj_mingw_crt/.lc_built: | obj_mingw_crt/.lc_configured
|
||||
cd obj_mingw_crt && $(MAKE) -j$(CPUS) $(MINGW_VARS)
|
||||
touch $@
|
||||
|
||||
obj_mingw_pthreads/.lc_configured: | obj_mingw_crt/.lc_built obj_mingw_pthreads src_mingw
|
||||
cd obj_mingw_pthreads && ../src_mingw/mingw-w64-libraries/winpthreads/configure $(FULL_MINGW_PTHREADS_CONFIG)
|
||||
touch $@
|
||||
|
||||
obj_mingw_pthreads/.lc_built: | obj_mingw_pthreads/.lc_configured
|
||||
cd obj_mingw_pthreads && $(MAKE) -j$(CPUS) $(MINGW_VARS)
|
||||
touch $@
|
||||
|
||||
obj_sysroot/.lc_libs_pthreads: | obj_mingw_pthreads/.lc_built
|
||||
cd obj_mingw_pthreads && $(MAKE) -j$(CPUS) $(MINGW_VARS) DESTDIR=$(CURDIR)/obj_sysroot/$(TARGET) install
|
||||
touch $@
|
||||
|
||||
obj_sysroot/.lc_libs_crt: | obj_mingw_crt/.lc_built
|
||||
cd obj_mingw_crt && $(MAKE) -j$(CPUS) $(MINGW_VARS) DESTDIR=$(CURDIR)/obj_sysroot/$(TARGET) install
|
||||
touch $@
|
||||
|
||||
install-mingw-headers: | obj_mingw_headers/.lc_configured
|
||||
cd obj_mingw_headers && $(MAKE) -j$(CPUS) $(MINGW_VARS) DESTDIR=$(DESTDIR)$(OUTPUT)$(SYSROOT) install
|
||||
|
||||
install-mingw-crt: | obj_mingw_crt/.lc_built
|
||||
cd obj_mingw_crt && $(MAKE) -j$(CPUS) $(MINGW_VARS) DESTDIR=$(DESTDIR)$(OUTPUT)$(SYSROOT) install
|
||||
|
||||
install-mingw-pthreads: | obj_mingw_pthreads/.lc_built
|
||||
cd obj_mingw_pthreads && $(MAKE) -j$(CPUS) $(MINGW_VARS) DESTDIR=$(DESTDIR)$(OUTPUT)$(SYSROOT) install
|
||||
|
||||
install-mingw: install-mingw-headers install-mingw-crt install-mingw-pthreads
|
||||
|
||||
ifneq ($(LINUX_SRCDIR),)
|
||||
TARGET_ARCH = $(firstword $(subst -, ,$(TARGET)))
|
||||
TARGET_ARCH_MANGLED = $(patsubst i%86,x86,$(patsubst aarch64%,arm64%,$(patsubst or1k%,openrisc%,$(TARGET_ARCH))))
|
||||
|
||||
@ -0,0 +1,59 @@
|
||||
diff -ur a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
--- a/bfd/elf32-arm.c 2020-04-15 17:46:10.564727832 -0500
|
||||
+++ b/bfd/elf32-arm.c 2020-04-16 15:26:30.908073105 -0500
|
||||
@@ -3607,6 +3607,18 @@
|
||||
/* Ensure that we have allocated bookkeeping structures for ABFD's local
|
||||
symbols. */
|
||||
|
||||
+static char *
|
||||
+elf32_arm_bfd_align (char *base, char *x, bfd_size_type align)
|
||||
+{
|
||||
+ bfd_size_type offset = x - base;
|
||||
+ bfd_size_type mod = offset % align;
|
||||
+ if (mod > 0)
|
||||
+ {
|
||||
+ offset += align - mod;
|
||||
+ }
|
||||
+ return base + offset;
|
||||
+}
|
||||
+
|
||||
static bfd_boolean
|
||||
elf32_arm_allocate_local_sym_info (bfd *abfd)
|
||||
{
|
||||
@@ -3615,9 +3627,10 @@
|
||||
bfd_size_type num_syms;
|
||||
bfd_size_type size;
|
||||
char *data;
|
||||
+ char *data_start;
|
||||
|
||||
num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
|
||||
- size = num_syms * (sizeof (bfd_signed_vma)
|
||||
+ size = (num_syms + 1) * (sizeof (bfd_signed_vma)
|
||||
+ sizeof (struct arm_local_iplt_info *)
|
||||
+ sizeof (bfd_vma)
|
||||
+ sizeof (char)
|
||||
@@ -3625,19 +3638,24 @@
|
||||
data = bfd_zalloc (abfd, size);
|
||||
if (data == NULL)
|
||||
return FALSE;
|
||||
+ data_start = data;
|
||||
|
||||
elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
|
||||
data += num_syms * sizeof (struct fdpic_local);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_signed_vma));
|
||||
elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
|
||||
data += num_syms * sizeof (bfd_signed_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (struct arm_local_iplt_info *));
|
||||
elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
|
||||
data += num_syms * sizeof (struct arm_local_iplt_info *);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_vma));
|
||||
elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
|
||||
data += num_syms * sizeof (bfd_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (char));
|
||||
elf32_arm_local_got_tls_type (abfd) = data;
|
||||
}
|
||||
return TRUE;
|
||||
584
patches/binutils-2.34/0001-j2-234.diff
Normal file
584
patches/binutils-2.34/0001-j2-234.diff
Normal file
@ -0,0 +1,584 @@
|
||||
diff -r -r -u bin1/bfd/archures.c bin2/bfd/archures.c
|
||||
--- bin1/bfd/archures.c 2020-02-22 18:43:09.093140003 -0600
|
||||
+++ bin2/bfd/archures.c 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/bfd-in2.h bin2/bfd/bfd-in2.h
|
||||
--- bin1/bfd/bfd-in2.h 2020-02-22 18:43:09.109140324 -0600
|
||||
+++ bin2/bfd/bfd-in2.h 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -1681,6 +1681,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/cpu-sh.c bin2/bfd/cpu-sh.c
|
||||
--- bin1/bfd/cpu-sh.c 2020-02-22 18:43:09.101140163 -0600
|
||||
+++ bin2/bfd/cpu-sh.c 2020-02-22 18:58:20.087400878 -0600
|
||||
@@ -63,7 +63,9 @@
|
||||
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", FALSE, arch_info_struct + 16),
|
||||
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", FALSE, arch_info_struct + 17),
|
||||
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", FALSE, arch_info_struct + 18),
|
||||
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, NULL)
|
||||
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, arch_info_struct + 19),
|
||||
+ N (bfd_mach_shj2, "j2", FALSE, arch_info_struct + 20),
|
||||
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", FALSE, NULL)
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -99,6 +101,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
diff -r -r -u bin1/binutils/readelf.c bin2/binutils/readelf.c
|
||||
--- bin1/binutils/readelf.c 2020-02-22 18:43:08.793133996 -0600
|
||||
+++ bin2/binutils/readelf.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -3556,6 +3556,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
diff -r -r -u bin1/gas/config/tc-aarch64.c bin2/gas/config/tc-aarch64.c
|
||||
--- bin1/gas/config/tc-aarch64.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-aarch64.c 2020-02-22 18:44:18.122522254 -0600
|
||||
@@ -250,7 +250,7 @@
|
||||
typedef struct
|
||||
{
|
||||
const char *template;
|
||||
- unsigned long value;
|
||||
+ uint32_t value;
|
||||
} asm_barrier_opt;
|
||||
|
||||
typedef struct
|
||||
diff -r -r -u bin1/gas/config/tc-sh.c bin2/gas/config/tc-sh.c
|
||||
--- bin1/gas/config/tc-sh.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-sh.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a.s bin2/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3e.s bin2/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3.s bin2/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a.s bin2/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4.s bin2/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/include/elf/sh.h bin2/include/elf/sh.h
|
||||
--- bin1/include/elf/sh.h 2020-02-22 18:43:08.761133356 -0600
|
||||
+++ bin2/include/elf/sh.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -r -r -u bin1/opcodes/sh-dis.c bin2/opcodes/sh-dis.c
|
||||
--- bin1/opcodes/sh-dis.c 2020-02-22 18:43:08.777133677 -0600
|
||||
+++ bin2/opcodes/sh-dis.c 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -860,6 +860,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
diff -r -r -u bin1/opcodes/sh-opc.h bin2/opcodes/sh-opc.h
|
||||
--- bin1/opcodes/sh-opc.h 2020-02-22 18:43:08.773133596 -0600
|
||||
+++ bin2/opcodes/sh-opc.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
32
patches/binutils-2.34/0001-skip-destructors-on-mingw.patch
Normal file
32
patches/binutils-2.34/0001-skip-destructors-on-mingw.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pep.sc binutils-2.32/ld/scripttempl/pep.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pep.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pep.sc 2019-06-02 12:26:01.212943752 +0200
|
||||
@@ -124,10 +124,8 @@
|
||||
LONG (0); LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1); LONG (-1);
|
||||
KEEP (*(.dtors));
|
||||
KEEP (*(.dtor));
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pe.sc binutils-2.32/ld/scripttempl/pe.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pe.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pe.sc 2019-06-02 12:27:03.104562647 +0200
|
||||
@@ -123,10 +123,8 @@
|
||||
LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1);
|
||||
KEEP(*(.dtors));
|
||||
KEEP(*(.dtor));
|
||||
249
patches/binutils-2.34/0002-or1k-32bithost-1.diff
Normal file
249
patches/binutils-2.34/0002-or1k-32bithost-1.diff
Normal file
@ -0,0 +1,249 @@
|
||||
From: Stafford Horne <shorne@gmail.com>
|
||||
To: GNU Binutils <binutils@sourceware.org>
|
||||
Cc: Openrisc <openrisc@lists.librecores.org>, dalias@libc.org, Stafford Horne <shorne@gmail.com>
|
||||
Subject: [PATCH 1/2] or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts
|
||||
Date: Wed, 11 Dec 2019 06:49:05 +0900
|
||||
|
||||
Reported by Rich Felker when building on 32-bit hosts. Backwards jump
|
||||
negative offsets were not calculated correctly due to improper 32-bit
|
||||
to 64-bit zero-extension. The 64-bit fields are present because we
|
||||
are mixing 32-bit and 64-bit architectures in our cpu descriptions.
|
||||
|
||||
Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture
|
||||
spec for 64-bit but no implementations or simulators. My thought is if
|
||||
we need them in the future we should do the proper work to support both
|
||||
32-bit and 64-bit implementations co-existing then.
|
||||
|
||||
cpu/ChangeLog:
|
||||
|
||||
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
|
||||
|
||||
PR 25184
|
||||
* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
|
||||
(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
|
||||
(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
|
||||
* or1kcommon.cpu (h-fdr): Remove hardware.
|
||||
* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
|
||||
(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
|
||||
(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
|
||||
(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
|
||||
(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
|
||||
---
|
||||
cpu/or1k.cpu | 35 +++----------------------
|
||||
cpu/or1kcommon.cpu | 14 ----------
|
||||
cpu/or1korfpx.cpu | 64 ----------------------------------------------
|
||||
3 files changed, 3 insertions(+), 110 deletions(-)
|
||||
|
||||
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
|
||||
index b796862d1b..9784f7a0fa 100644
|
||||
--- a/cpu/or1k.cpu
|
||||
+++ b/cpu/or1k.cpu
|
||||
@@ -31,7 +31,7 @@
|
||||
(comment "OpenRISC 1000")
|
||||
(default-alignment aligned)
|
||||
(insn-lsb0? #t)
|
||||
- (machs or32 or32nd or64 or64nd)
|
||||
+ (machs or32 or32nd)
|
||||
(isas openrisc)
|
||||
)
|
||||
|
||||
@@ -44,10 +44,8 @@
|
||||
)
|
||||
|
||||
(define-pmacro OR32-MACHS or32,or32nd)
|
||||
-(define-pmacro OR64-MACHS or64,or64nd)
|
||||
-(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
|
||||
-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
|
||||
-(define-pmacro ORFPX64-MACHS or64,or64nd)
|
||||
+(define-pmacro ORBIS-MACHS or32,or32nd)
|
||||
+(define-pmacro ORFPX32-MACHS or32,or32nd)
|
||||
(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
|
||||
|
||||
(define-attr
|
||||
@@ -100,33 +98,6 @@
|
||||
)
|
||||
)
|
||||
|
||||
-(if (keep-mach? (or64 or64nd))
|
||||
- (begin
|
||||
- (define-cpu
|
||||
- (name or1k64bf)
|
||||
- (comment "OpenRISC 1000 64-bit CPU family")
|
||||
- (insn-endian big)
|
||||
- (data-endian big)
|
||||
- (word-bitsize 64)
|
||||
- (file-transform "64")
|
||||
- )
|
||||
-
|
||||
- (define-mach
|
||||
- (name or64)
|
||||
- (comment "Generic OpenRISC 1000 64-bit CPU")
|
||||
- (cpu or1k64bf)
|
||||
- (bfd-name "or1k64")
|
||||
- )
|
||||
-
|
||||
- (define-mach
|
||||
- (name or64nd)
|
||||
- (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
|
||||
- (cpu or1k64bf)
|
||||
- (bfd-name "or1k64nd")
|
||||
- )
|
||||
- )
|
||||
- )
|
||||
-
|
||||
(include "or1kcommon.cpu")
|
||||
(include "or1korbis.cpu")
|
||||
(include "or1korfpx.cpu")
|
||||
diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu
|
||||
index 65154407df..9f102c93a1 100644
|
||||
--- a/cpu/or1kcommon.cpu
|
||||
+++ b/cpu/or1kcommon.cpu
|
||||
@@ -114,20 +114,6 @@
|
||||
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
|
||||
)
|
||||
|
||||
-;
|
||||
-; Hardware: virtual registerts for FPU (double precision)
|
||||
-; mapped to GPRs
|
||||
-;
|
||||
-(define-hardware
|
||||
- (name h-fdr)
|
||||
- (comment "or64 floating point registers (double, virtual)")
|
||||
- (attrs VIRTUAL (MACH ORFPX64-MACHS))
|
||||
- (type register DF (32))
|
||||
- (indices keyword "" REG-INDICES)
|
||||
- (get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
|
||||
- (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
|
||||
- )
|
||||
-
|
||||
;
|
||||
; Register pairs are offset by 2 for registers r16 and above. This is to
|
||||
; be able to allow registers to be call saved in GCC across function calls.
|
||||
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
|
||||
index f43522f2e6..0bd469cff5 100644
|
||||
--- a/cpu/or1korfpx.cpu
|
||||
+++ b/cpu/or1korfpx.cpu
|
||||
@@ -84,10 +84,6 @@
|
||||
(dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2)
|
||||
(dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3)
|
||||
|
||||
-(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
|
||||
-(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2)
|
||||
-(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3)
|
||||
-
|
||||
(define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
|
||||
(begin
|
||||
(define-multi-ifield
|
||||
@@ -152,14 +148,6 @@
|
||||
(set SF rDSF (mnemonic SF rASF rBSF))
|
||||
()
|
||||
)
|
||||
- (dni (.sym lf- mnemonic -d)
|
||||
- (.str "lf." mnemonic ".d reg/reg/reg")
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
|
||||
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
|
||||
- (set DF rDDF (mnemonic DF rADF rBDF))
|
||||
- ()
|
||||
- )
|
||||
(dni (.sym lf- mnemonic -d32)
|
||||
(.str "lf." mnemonic ".d regpair/regpair/regpair")
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -185,15 +173,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-rem-d
|
||||
- "lf.rem.d reg/reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.rem.d $rDDF,$rADF,$rBDF"
|
||||
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
|
||||
- (set DF rDDF (rem DF rADF rBDF))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-rem-d32
|
||||
"lf.rem.d regpair/regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -221,15 +200,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-itof-d
|
||||
- "lf.itof.d reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.itof.d $rDDF,$rA"
|
||||
- (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
|
||||
- (set DF rDDF (float DF (get-rounding-mode) rA))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-itof-d32
|
||||
"lf.itof.d regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -248,15 +218,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-ftoi-d
|
||||
- "lf.ftoi.d reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.ftoi.d $rD,$rADF"
|
||||
- (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
|
||||
- (set WI rD (fix WI (get-rounding-mode) rADF))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-ftoi-d32
|
||||
"lf.ftoi.d regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -276,14 +237,6 @@
|
||||
(symantics rtx-mnemonic SF rASF rBSF)
|
||||
()
|
||||
)
|
||||
- (dni (.sym lf-sf mnemonic -d)
|
||||
- (.str "lf.sf" mnemonic ".d reg/reg")
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- (.str "lf.sf" mnemonic ".d $rADF,$rBDF")
|
||||
- (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
|
||||
- (symantics rtx-mnemonic DF rADF rBDF)
|
||||
- ()
|
||||
- )
|
||||
(dni (.sym lf-sf mnemonic -d32)
|
||||
(.str "lf.sf" mnemonic ".d regpair/regpair")
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -336,15 +289,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-madd-d
|
||||
- "lf.madd.d reg/reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.madd.d $rDDF,$rADF,$rBDF"
|
||||
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
|
||||
- (set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-madd-d32
|
||||
"lf.madd.d regpair/regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -364,14 +308,6 @@
|
||||
(nop)
|
||||
()
|
||||
)
|
||||
- (dni (.sym "lf-cust" cust-num "-d")
|
||||
- (.str "lf.cust" cust-num ".d")
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- (.str "lf.cust" cust-num ".d")
|
||||
- (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
|
||||
- (nop)
|
||||
- ()
|
||||
- )
|
||||
(dni (.sym "lf-cust" cust-num "-d32")
|
||||
(.str "lf.cust" cust-num ".d")
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
--
|
||||
2.21.0
|
||||
|
||||
|
||||
4299
patches/binutils-2.34/0003-or1k-32bithost-2.diff
Normal file
4299
patches/binutils-2.34/0003-or1k-32bithost-2.diff
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,59 @@
|
||||
diff -ur a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
--- a/bfd/elf32-arm.c 2020-04-15 17:46:10.564727832 -0500
|
||||
+++ b/bfd/elf32-arm.c 2020-04-16 15:26:30.908073105 -0500
|
||||
@@ -3607,6 +3607,18 @@
|
||||
/* Ensure that we have allocated bookkeeping structures for ABFD's local
|
||||
symbols. */
|
||||
|
||||
+static char *
|
||||
+elf32_arm_bfd_align (char *base, char *x, bfd_size_type align)
|
||||
+{
|
||||
+ bfd_size_type offset = x - base;
|
||||
+ bfd_size_type mod = offset % align;
|
||||
+ if (mod > 0)
|
||||
+ {
|
||||
+ offset += align - mod;
|
||||
+ }
|
||||
+ return base + offset;
|
||||
+}
|
||||
+
|
||||
static bfd_boolean
|
||||
elf32_arm_allocate_local_sym_info (bfd *abfd)
|
||||
{
|
||||
@@ -3615,9 +3627,10 @@
|
||||
bfd_size_type num_syms;
|
||||
bfd_size_type size;
|
||||
char *data;
|
||||
+ char *data_start;
|
||||
|
||||
num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
|
||||
- size = num_syms * (sizeof (bfd_signed_vma)
|
||||
+ size = (num_syms + 1) * (sizeof (bfd_signed_vma)
|
||||
+ sizeof (struct arm_local_iplt_info *)
|
||||
+ sizeof (bfd_vma)
|
||||
+ sizeof (char)
|
||||
@@ -3625,19 +3638,24 @@
|
||||
data = bfd_zalloc (abfd, size);
|
||||
if (data == NULL)
|
||||
return FALSE;
|
||||
+ data_start = data;
|
||||
|
||||
elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
|
||||
data += num_syms * sizeof (struct fdpic_local);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_signed_vma));
|
||||
elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
|
||||
data += num_syms * sizeof (bfd_signed_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (struct arm_local_iplt_info *));
|
||||
elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
|
||||
data += num_syms * sizeof (struct arm_local_iplt_info *);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_vma));
|
||||
elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
|
||||
data += num_syms * sizeof (bfd_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (char));
|
||||
elf32_arm_local_got_tls_type (abfd) = data;
|
||||
}
|
||||
return TRUE;
|
||||
584
patches/binutils-2.35.1/0001-j2-234.diff
Normal file
584
patches/binutils-2.35.1/0001-j2-234.diff
Normal file
@ -0,0 +1,584 @@
|
||||
diff -r -r -u bin1/bfd/archures.c bin2/bfd/archures.c
|
||||
--- bin1/bfd/archures.c 2020-02-22 18:43:09.093140003 -0600
|
||||
+++ bin2/bfd/archures.c 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/bfd-in2.h bin2/bfd/bfd-in2.h
|
||||
--- bin1/bfd/bfd-in2.h 2020-02-22 18:43:09.109140324 -0600
|
||||
+++ bin2/bfd/bfd-in2.h 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -1681,6 +1681,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/cpu-sh.c bin2/bfd/cpu-sh.c
|
||||
--- bin1/bfd/cpu-sh.c 2020-02-22 18:43:09.101140163 -0600
|
||||
+++ bin2/bfd/cpu-sh.c 2020-02-22 18:58:20.087400878 -0600
|
||||
@@ -63,7 +63,9 @@
|
||||
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", FALSE, arch_info_struct + 16),
|
||||
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", FALSE, arch_info_struct + 17),
|
||||
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", FALSE, arch_info_struct + 18),
|
||||
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, NULL)
|
||||
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, arch_info_struct + 19),
|
||||
+ N (bfd_mach_shj2, "j2", FALSE, arch_info_struct + 20),
|
||||
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", FALSE, NULL)
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -99,6 +101,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
diff -r -r -u bin1/binutils/readelf.c bin2/binutils/readelf.c
|
||||
--- bin1/binutils/readelf.c 2020-02-22 18:43:08.793133996 -0600
|
||||
+++ bin2/binutils/readelf.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -3556,6 +3556,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
diff -r -r -u bin1/gas/config/tc-aarch64.c bin2/gas/config/tc-aarch64.c
|
||||
--- bin1/gas/config/tc-aarch64.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-aarch64.c 2020-02-22 18:44:18.122522254 -0600
|
||||
@@ -250,7 +250,7 @@
|
||||
typedef struct
|
||||
{
|
||||
const char *template;
|
||||
- unsigned long value;
|
||||
+ uint32_t value;
|
||||
} asm_barrier_opt;
|
||||
|
||||
typedef struct
|
||||
diff -r -r -u bin1/gas/config/tc-sh.c bin2/gas/config/tc-sh.c
|
||||
--- bin1/gas/config/tc-sh.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-sh.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a.s bin2/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3e.s bin2/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3.s bin2/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a.s bin2/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4.s bin2/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/include/elf/sh.h bin2/include/elf/sh.h
|
||||
--- bin1/include/elf/sh.h 2020-02-22 18:43:08.761133356 -0600
|
||||
+++ bin2/include/elf/sh.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -r -r -u bin1/opcodes/sh-dis.c bin2/opcodes/sh-dis.c
|
||||
--- bin1/opcodes/sh-dis.c 2020-02-22 18:43:08.777133677 -0600
|
||||
+++ bin2/opcodes/sh-dis.c 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -860,6 +860,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
diff -r -r -u bin1/opcodes/sh-opc.h bin2/opcodes/sh-opc.h
|
||||
--- bin1/opcodes/sh-opc.h 2020-02-22 18:43:08.773133596 -0600
|
||||
+++ bin2/opcodes/sh-opc.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
32
patches/binutils-2.35.1/0001-skip-destructors-on-mingw.patch
Normal file
32
patches/binutils-2.35.1/0001-skip-destructors-on-mingw.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pep.sc binutils-2.32/ld/scripttempl/pep.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pep.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pep.sc 2019-06-02 12:26:01.212943752 +0200
|
||||
@@ -124,10 +124,8 @@
|
||||
LONG (0); LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1); LONG (-1);
|
||||
KEEP (*(.dtors));
|
||||
KEEP (*(.dtor));
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pe.sc binutils-2.32/ld/scripttempl/pe.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pe.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pe.sc 2019-06-02 12:27:03.104562647 +0200
|
||||
@@ -123,10 +123,8 @@
|
||||
LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1);
|
||||
KEEP(*(.dtors));
|
||||
KEEP(*(.dtor));
|
||||
@ -0,0 +1,59 @@
|
||||
diff -ur a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
--- a/bfd/elf32-arm.c 2020-04-15 17:46:10.564727832 -0500
|
||||
+++ b/bfd/elf32-arm.c 2020-04-16 15:26:30.908073105 -0500
|
||||
@@ -3607,6 +3607,18 @@
|
||||
/* Ensure that we have allocated bookkeeping structures for ABFD's local
|
||||
symbols. */
|
||||
|
||||
+static char *
|
||||
+elf32_arm_bfd_align (char *base, char *x, bfd_size_type align)
|
||||
+{
|
||||
+ bfd_size_type offset = x - base;
|
||||
+ bfd_size_type mod = offset % align;
|
||||
+ if (mod > 0)
|
||||
+ {
|
||||
+ offset += align - mod;
|
||||
+ }
|
||||
+ return base + offset;
|
||||
+}
|
||||
+
|
||||
static bfd_boolean
|
||||
elf32_arm_allocate_local_sym_info (bfd *abfd)
|
||||
{
|
||||
@@ -3615,9 +3627,10 @@
|
||||
bfd_size_type num_syms;
|
||||
bfd_size_type size;
|
||||
char *data;
|
||||
+ char *data_start;
|
||||
|
||||
num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
|
||||
- size = num_syms * (sizeof (bfd_signed_vma)
|
||||
+ size = (num_syms + 1) * (sizeof (bfd_signed_vma)
|
||||
+ sizeof (struct arm_local_iplt_info *)
|
||||
+ sizeof (bfd_vma)
|
||||
+ sizeof (char)
|
||||
@@ -3625,19 +3638,24 @@
|
||||
data = bfd_zalloc (abfd, size);
|
||||
if (data == NULL)
|
||||
return FALSE;
|
||||
+ data_start = data;
|
||||
|
||||
elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
|
||||
data += num_syms * sizeof (struct fdpic_local);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_signed_vma));
|
||||
elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
|
||||
data += num_syms * sizeof (bfd_signed_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (struct arm_local_iplt_info *));
|
||||
elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
|
||||
data += num_syms * sizeof (struct arm_local_iplt_info *);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_vma));
|
||||
elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
|
||||
data += num_syms * sizeof (bfd_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (char));
|
||||
elf32_arm_local_got_tls_type (abfd) = data;
|
||||
}
|
||||
return TRUE;
|
||||
572
patches/binutils-2.35.2/0001-j2-234.diff
Normal file
572
patches/binutils-2.35.2/0001-j2-234.diff
Normal file
@ -0,0 +1,572 @@
|
||||
diff -r -r -u bin1/bfd/archures.c bin2/bfd/archures.c
|
||||
--- bin1/bfd/archures.c 2020-02-22 18:43:09.093140003 -0600
|
||||
+++ bin2/bfd/archures.c 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/bfd-in2.h bin2/bfd/bfd-in2.h
|
||||
--- bin1/bfd/bfd-in2.h 2020-02-22 18:43:09.109140324 -0600
|
||||
+++ bin2/bfd/bfd-in2.h 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -1681,6 +1681,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/cpu-sh.c bin2/bfd/cpu-sh.c
|
||||
--- bin1/bfd/cpu-sh.c 2020-02-22 18:43:09.101140163 -0600
|
||||
+++ bin2/bfd/cpu-sh.c 2020-02-22 18:58:20.087400878 -0600
|
||||
@@ -63,7 +63,9 @@
|
||||
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", FALSE, arch_info_struct + 16),
|
||||
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", FALSE, arch_info_struct + 17),
|
||||
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", FALSE, arch_info_struct + 18),
|
||||
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, NULL)
|
||||
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, arch_info_struct + 19),
|
||||
+ N (bfd_mach_shj2, "j2", FALSE, arch_info_struct + 20),
|
||||
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", FALSE, NULL)
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -99,6 +101,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
diff -r -r -u bin1/binutils/readelf.c bin2/binutils/readelf.c
|
||||
--- bin1/binutils/readelf.c 2020-02-22 18:43:08.793133996 -0600
|
||||
+++ bin2/binutils/readelf.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -3556,6 +3556,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
diff -r -r -u bin1/gas/config/tc-sh.c bin2/gas/config/tc-sh.c
|
||||
--- bin1/gas/config/tc-sh.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-sh.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a.s bin2/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3e.s bin2/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3.s bin2/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a.s bin2/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4.s bin2/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/include/elf/sh.h bin2/include/elf/sh.h
|
||||
--- bin1/include/elf/sh.h 2020-02-22 18:43:08.761133356 -0600
|
||||
+++ bin2/include/elf/sh.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -r -r -u bin1/opcodes/sh-dis.c bin2/opcodes/sh-dis.c
|
||||
--- bin1/opcodes/sh-dis.c 2020-02-22 18:43:08.777133677 -0600
|
||||
+++ bin2/opcodes/sh-dis.c 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -860,6 +860,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
diff -r -r -u bin1/opcodes/sh-opc.h bin2/opcodes/sh-opc.h
|
||||
--- bin1/opcodes/sh-opc.h 2020-02-22 18:43:08.773133596 -0600
|
||||
+++ bin2/opcodes/sh-opc.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
32
patches/binutils-2.35.2/0001-skip-destructors-on-mingw.patch
Normal file
32
patches/binutils-2.35.2/0001-skip-destructors-on-mingw.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pep.sc binutils-2.32/ld/scripttempl/pep.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pep.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pep.sc 2019-06-02 12:26:01.212943752 +0200
|
||||
@@ -124,10 +124,8 @@
|
||||
LONG (0); LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1); LONG (-1);
|
||||
KEEP (*(.dtors));
|
||||
KEEP (*(.dtor));
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pe.sc binutils-2.32/ld/scripttempl/pe.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pe.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pe.sc 2019-06-02 12:27:03.104562647 +0200
|
||||
@@ -123,10 +123,8 @@
|
||||
LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1);
|
||||
KEEP(*(.dtors));
|
||||
KEEP(*(.dtor));
|
||||
@ -0,0 +1,59 @@
|
||||
diff -ur a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
--- a/bfd/elf32-arm.c 2020-04-15 17:46:10.564727832 -0500
|
||||
+++ b/bfd/elf32-arm.c 2020-04-16 15:26:30.908073105 -0500
|
||||
@@ -3607,6 +3607,18 @@
|
||||
/* Ensure that we have allocated bookkeeping structures for ABFD's local
|
||||
symbols. */
|
||||
|
||||
+static char *
|
||||
+elf32_arm_bfd_align (char *base, char *x, bfd_size_type align)
|
||||
+{
|
||||
+ bfd_size_type offset = x - base;
|
||||
+ bfd_size_type mod = offset % align;
|
||||
+ if (mod > 0)
|
||||
+ {
|
||||
+ offset += align - mod;
|
||||
+ }
|
||||
+ return base + offset;
|
||||
+}
|
||||
+
|
||||
static bfd_boolean
|
||||
elf32_arm_allocate_local_sym_info (bfd *abfd)
|
||||
{
|
||||
@@ -3615,9 +3627,10 @@
|
||||
bfd_size_type num_syms;
|
||||
bfd_size_type size;
|
||||
char *data;
|
||||
+ char *data_start;
|
||||
|
||||
num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
|
||||
- size = num_syms * (sizeof (bfd_signed_vma)
|
||||
+ size = (num_syms + 1) * (sizeof (bfd_signed_vma)
|
||||
+ sizeof (struct arm_local_iplt_info *)
|
||||
+ sizeof (bfd_vma)
|
||||
+ sizeof (char)
|
||||
@@ -3625,19 +3638,24 @@
|
||||
data = bfd_zalloc (abfd, size);
|
||||
if (data == NULL)
|
||||
return FALSE;
|
||||
+ data_start = data;
|
||||
|
||||
elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
|
||||
data += num_syms * sizeof (struct fdpic_local);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_signed_vma));
|
||||
elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
|
||||
data += num_syms * sizeof (bfd_signed_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (struct arm_local_iplt_info *));
|
||||
elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
|
||||
data += num_syms * sizeof (struct arm_local_iplt_info *);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (bfd_vma));
|
||||
elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
|
||||
data += num_syms * sizeof (bfd_vma);
|
||||
|
||||
+ data = elf32_arm_bfd_align(data_start, data, sizeof (char));
|
||||
elf32_arm_local_got_tls_type (abfd) = data;
|
||||
}
|
||||
return TRUE;
|
||||
584
patches/binutils-2.35/0001-j2-234.diff
Normal file
584
patches/binutils-2.35/0001-j2-234.diff
Normal file
@ -0,0 +1,584 @@
|
||||
diff -r -r -u bin1/bfd/archures.c bin2/bfd/archures.c
|
||||
--- bin1/bfd/archures.c 2020-02-22 18:43:09.093140003 -0600
|
||||
+++ bin2/bfd/archures.c 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/bfd-in2.h bin2/bfd/bfd-in2.h
|
||||
--- bin1/bfd/bfd-in2.h 2020-02-22 18:43:09.109140324 -0600
|
||||
+++ bin2/bfd/bfd-in2.h 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -1681,6 +1681,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/cpu-sh.c bin2/bfd/cpu-sh.c
|
||||
--- bin1/bfd/cpu-sh.c 2020-02-22 18:43:09.101140163 -0600
|
||||
+++ bin2/bfd/cpu-sh.c 2020-02-22 18:58:20.087400878 -0600
|
||||
@@ -63,7 +63,9 @@
|
||||
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", FALSE, arch_info_struct + 16),
|
||||
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", FALSE, arch_info_struct + 17),
|
||||
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", FALSE, arch_info_struct + 18),
|
||||
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, NULL)
|
||||
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, arch_info_struct + 19),
|
||||
+ N (bfd_mach_shj2, "j2", FALSE, arch_info_struct + 20),
|
||||
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", FALSE, NULL)
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -99,6 +101,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
diff -r -r -u bin1/binutils/readelf.c bin2/binutils/readelf.c
|
||||
--- bin1/binutils/readelf.c 2020-02-22 18:43:08.793133996 -0600
|
||||
+++ bin2/binutils/readelf.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -3556,6 +3556,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
diff -r -r -u bin1/gas/config/tc-aarch64.c bin2/gas/config/tc-aarch64.c
|
||||
--- bin1/gas/config/tc-aarch64.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-aarch64.c 2020-02-22 18:44:18.122522254 -0600
|
||||
@@ -250,7 +250,7 @@
|
||||
typedef struct
|
||||
{
|
||||
const char *template;
|
||||
- unsigned long value;
|
||||
+ uint32_t value;
|
||||
} asm_barrier_opt;
|
||||
|
||||
typedef struct
|
||||
diff -r -r -u bin1/gas/config/tc-sh.c bin2/gas/config/tc-sh.c
|
||||
--- bin1/gas/config/tc-sh.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-sh.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a.s bin2/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3e.s bin2/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3.s bin2/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a.s bin2/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4.s bin2/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/include/elf/sh.h bin2/include/elf/sh.h
|
||||
--- bin1/include/elf/sh.h 2020-02-22 18:43:08.761133356 -0600
|
||||
+++ bin2/include/elf/sh.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -r -r -u bin1/opcodes/sh-dis.c bin2/opcodes/sh-dis.c
|
||||
--- bin1/opcodes/sh-dis.c 2020-02-22 18:43:08.777133677 -0600
|
||||
+++ bin2/opcodes/sh-dis.c 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -860,6 +860,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
diff -r -r -u bin1/opcodes/sh-opc.h bin2/opcodes/sh-opc.h
|
||||
--- bin1/opcodes/sh-opc.h 2020-02-22 18:43:08.773133596 -0600
|
||||
+++ bin2/opcodes/sh-opc.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
32
patches/binutils-2.35/0001-skip-destructors-on-mingw.patch
Normal file
32
patches/binutils-2.35/0001-skip-destructors-on-mingw.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pep.sc binutils-2.32/ld/scripttempl/pep.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pep.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pep.sc 2019-06-02 12:26:01.212943752 +0200
|
||||
@@ -124,10 +124,8 @@
|
||||
LONG (0); LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1); LONG (-1);
|
||||
KEEP (*(.dtors));
|
||||
KEEP (*(.dtor));
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pe.sc binutils-2.32/ld/scripttempl/pe.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pe.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pe.sc 2019-06-02 12:27:03.104562647 +0200
|
||||
@@ -123,10 +123,8 @@
|
||||
LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1);
|
||||
KEEP(*(.dtors));
|
||||
KEEP(*(.dtor));
|
||||
572
patches/binutils-2.36.1/0001-j2-234.diff
Normal file
572
patches/binutils-2.36.1/0001-j2-234.diff
Normal file
@ -0,0 +1,572 @@
|
||||
diff -r -r -u bin1/bfd/archures.c bin2/bfd/archures.c
|
||||
--- bin1/bfd/archures.c 2020-02-22 18:43:09.093140003 -0600
|
||||
+++ bin2/bfd/archures.c 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/bfd-in2.h bin2/bfd/bfd-in2.h
|
||||
--- bin1/bfd/bfd-in2.h 2020-02-22 18:43:09.109140324 -0600
|
||||
+++ bin2/bfd/bfd-in2.h 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -1681,6 +1681,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/cpu-sh.c bin2/bfd/cpu-sh.c
|
||||
--- bin1/bfd/cpu-sh.c 2020-02-22 18:43:09.101140163 -0600
|
||||
+++ bin2/bfd/cpu-sh.c 2020-02-22 18:58:20.087400878 -0600
|
||||
@@ -63,7 +63,9 @@
|
||||
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", FALSE, arch_info_struct + 16),
|
||||
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", FALSE, arch_info_struct + 17),
|
||||
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", FALSE, arch_info_struct + 18),
|
||||
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, NULL)
|
||||
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, arch_info_struct + 19),
|
||||
+ N (bfd_mach_shj2, "j2", FALSE, arch_info_struct + 20),
|
||||
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", FALSE, NULL)
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -99,6 +101,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
diff -r -r -u bin1/binutils/readelf.c bin2/binutils/readelf.c
|
||||
--- bin1/binutils/readelf.c 2020-02-22 18:43:08.793133996 -0600
|
||||
+++ bin2/binutils/readelf.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -3556,6 +3556,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
diff -r -r -u bin1/gas/config/tc-sh.c bin2/gas/config/tc-sh.c
|
||||
--- bin1/gas/config/tc-sh.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-sh.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a.s bin2/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3e.s bin2/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3.s bin2/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a.s bin2/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4.s bin2/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/include/elf/sh.h bin2/include/elf/sh.h
|
||||
--- bin1/include/elf/sh.h 2020-02-22 18:43:08.761133356 -0600
|
||||
+++ bin2/include/elf/sh.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -r -r -u bin1/opcodes/sh-dis.c bin2/opcodes/sh-dis.c
|
||||
--- bin1/opcodes/sh-dis.c 2020-02-22 18:43:08.777133677 -0600
|
||||
+++ bin2/opcodes/sh-dis.c 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -860,6 +860,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
diff -r -r -u bin1/opcodes/sh-opc.h bin2/opcodes/sh-opc.h
|
||||
--- bin1/opcodes/sh-opc.h 2020-02-22 18:43:08.773133596 -0600
|
||||
+++ bin2/opcodes/sh-opc.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
32
patches/binutils-2.36.1/0001-skip-destructors-on-mingw.patch
Normal file
32
patches/binutils-2.36.1/0001-skip-destructors-on-mingw.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pep.sc binutils-2.32/ld/scripttempl/pep.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pep.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pep.sc 2019-06-02 12:26:01.212943752 +0200
|
||||
@@ -124,10 +124,8 @@
|
||||
LONG (0); LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1); LONG (-1);
|
||||
KEEP (*(.dtors));
|
||||
KEEP (*(.dtor));
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pe.sc binutils-2.32/ld/scripttempl/pe.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pe.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pe.sc 2019-06-02 12:27:03.104562647 +0200
|
||||
@@ -123,10 +123,8 @@
|
||||
LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1);
|
||||
KEEP(*(.dtors));
|
||||
KEEP(*(.dtor));
|
||||
572
patches/binutils-2.36/0001-j2-234.diff
Normal file
572
patches/binutils-2.36/0001-j2-234.diff
Normal file
@ -0,0 +1,572 @@
|
||||
diff -r -r -u bin1/bfd/archures.c bin2/bfd/archures.c
|
||||
--- bin1/bfd/archures.c 2020-02-22 18:43:09.093140003 -0600
|
||||
+++ bin2/bfd/archures.c 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/bfd-in2.h bin2/bfd/bfd-in2.h
|
||||
--- bin1/bfd/bfd-in2.h 2020-02-22 18:43:09.109140324 -0600
|
||||
+++ bin2/bfd/bfd-in2.h 2020-02-22 18:46:08.880740788 -0600
|
||||
@@ -1681,6 +1681,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
diff -r -r -u bin1/bfd/cpu-sh.c bin2/bfd/cpu-sh.c
|
||||
--- bin1/bfd/cpu-sh.c 2020-02-22 18:43:09.101140163 -0600
|
||||
+++ bin2/bfd/cpu-sh.c 2020-02-22 18:58:20.087400878 -0600
|
||||
@@ -63,7 +63,9 @@
|
||||
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", FALSE, arch_info_struct + 16),
|
||||
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", FALSE, arch_info_struct + 17),
|
||||
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", FALSE, arch_info_struct + 18),
|
||||
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, NULL)
|
||||
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, arch_info_struct + 19),
|
||||
+ N (bfd_mach_shj2, "j2", FALSE, arch_info_struct + 20),
|
||||
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", FALSE, NULL)
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -99,6 +101,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
diff -r -r -u bin1/binutils/readelf.c bin2/binutils/readelf.c
|
||||
--- bin1/binutils/readelf.c 2020-02-22 18:43:08.793133996 -0600
|
||||
+++ bin2/binutils/readelf.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -3556,6 +3556,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
diff -r -r -u bin1/gas/config/tc-sh.c bin2/gas/config/tc-sh.c
|
||||
--- bin1/gas/config/tc-sh.c 2020-02-22 18:43:08.917136479 -0600
|
||||
+++ bin2/gas/config/tc-sh.c 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2020-02-22 18:46:08.884740869 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh2a.s bin2/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh2a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3e.s bin2/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3e.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3-nommu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh3.s bin2/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh3.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4a.s bin2/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4a.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:43:09.021138561 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/gas/testsuite/gas/sh/arch/sh4.s bin2/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- bin1/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:43:09.017138482 -0600
|
||||
+++ bin2/gas/testsuite/gas/sh/arch/sh4.s 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -r -r -u bin1/include/elf/sh.h bin2/include/elf/sh.h
|
||||
--- bin1/include/elf/sh.h 2020-02-22 18:43:08.761133356 -0600
|
||||
+++ bin2/include/elf/sh.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -r -r -u bin1/opcodes/sh-dis.c bin2/opcodes/sh-dis.c
|
||||
--- bin1/opcodes/sh-dis.c 2020-02-22 18:43:08.777133677 -0600
|
||||
+++ bin2/opcodes/sh-dis.c 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -860,6 +860,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
diff -r -r -u bin1/opcodes/sh-opc.h bin2/opcodes/sh-opc.h
|
||||
--- bin1/opcodes/sh-opc.h 2020-02-22 18:43:08.773133596 -0600
|
||||
+++ bin2/opcodes/sh-opc.h 2020-02-22 18:46:08.888740948 -0600
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
32
patches/binutils-2.36/0001-skip-destructors-on-mingw.patch
Normal file
32
patches/binutils-2.36/0001-skip-destructors-on-mingw.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pep.sc binutils-2.32/ld/scripttempl/pep.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pep.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pep.sc 2019-06-02 12:26:01.212943752 +0200
|
||||
@@ -124,10 +124,8 @@
|
||||
LONG (0); LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1); LONG (-1);
|
||||
KEEP (*(.dtors));
|
||||
KEEP (*(.dtor));
|
||||
diff -ru binutils-2.32-orig/ld/scripttempl/pe.sc binutils-2.32/ld/scripttempl/pe.sc
|
||||
--- binutils-2.32-orig/ld/scripttempl/pe.sc 2019-01-19 17:01:33.000000000 +0100
|
||||
+++ binutils-2.32/ld/scripttempl/pe.sc 2019-06-02 12:27:03.104562647 +0200
|
||||
@@ -123,10 +123,8 @@
|
||||
LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1);
|
||||
KEEP(*(.dtors));
|
||||
KEEP(*(.dtor));
|
||||
572
patches/binutils-2.37/0001-j2-234.diff
Normal file
572
patches/binutils-2.37/0001-j2-234.diff
Normal file
@ -0,0 +1,572 @@
|
||||
diff -ur a/bfd/archures.c b/bfd/archures.c
|
||||
--- a/bfd/archures.c 2021-07-08 06:37:19.000000000 -0500
|
||||
+++ b/bfd/archures.c 2021-08-28 13:06:15.018055475 -0500
|
||||
@@ -293,6 +293,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
diff -ur a/bfd/bfd-in2.h b/bfd/bfd-in2.h
|
||||
--- a/bfd/bfd-in2.h 2021-07-08 06:37:19.000000000 -0500
|
||||
+++ b/bfd/bfd-in2.h 2021-08-28 13:06:15.018055475 -0500
|
||||
@@ -1670,6 +1670,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
diff -ur a/bfd/cpu-sh.c b/bfd/cpu-sh.c
|
||||
--- a/bfd/cpu-sh.c 2021-07-08 06:37:19.000000000 -0500
|
||||
+++ b/bfd/cpu-sh.c 2021-08-28 13:06:15.018055475 -0500
|
||||
@@ -63,7 +63,9 @@
|
||||
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", false, arch_info_struct + 16),
|
||||
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", false, arch_info_struct + 17),
|
||||
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", false, arch_info_struct + 18),
|
||||
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, NULL)
|
||||
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, arch_info_struct + 19),
|
||||
+ N (bfd_mach_shj2, "j2", false, arch_info_struct + 20),
|
||||
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", false, NULL)
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -99,6 +101,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
diff -ur a/binutils/readelf.c b/binutils/readelf.c
|
||||
--- a/binutils/readelf.c 2021-07-08 06:37:19.000000000 -0500
|
||||
+++ b/binutils/readelf.c 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -3729,6 +3729,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
diff -ur a/gas/config/tc-sh.c b/gas/config/tc-sh.c
|
||||
--- a/gas/config/tc-sh.c 2021-07-08 06:37:19.000000000 -0500
|
||||
+++ b/gas/config/tc-sh.c 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh2a.s b/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh2a.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh2a.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh3-dsp.s b/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh3-dsp.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh3e.s b/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh3e.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh3e.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh3-nommu.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh3.s b/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh3.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh3.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh4al-dsp.s b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh4a.s b/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh4a.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh4a.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh4-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/gas/testsuite/gas/sh/arch/sh4.s b/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- a/gas/testsuite/gas/sh/arch/sh4.s 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/gas/testsuite/gas/sh/arch/sh4.s 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur a/include/elf/sh.h b/include/elf/sh.h
|
||||
--- a/include/elf/sh.h 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/include/elf/sh.h 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -ur a/opcodes/sh-dis.c b/opcodes/sh-dis.c
|
||||
--- a/opcodes/sh-dis.c 2021-07-08 06:37:21.000000000 -0500
|
||||
+++ b/opcodes/sh-dis.c 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -864,6 +864,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
diff -ur a/opcodes/sh-opc.h b/opcodes/sh-opc.h
|
||||
--- a/opcodes/sh-opc.h 2021-07-08 06:37:21.000000000 -0500
|
||||
+++ b/opcodes/sh-opc.h 2021-08-28 13:06:15.022055532 -0500
|
||||
@@ -192,7 +192,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -216,9 +217,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -256,6 +259,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -320,7 +325,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -346,6 +352,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -714,9 +726,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1194,7 +1206,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
32
patches/binutils-2.37/0001-skip-destructors-on-mingw.patch
Normal file
32
patches/binutils-2.37/0001-skip-destructors-on-mingw.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff -ur a/ld/scripttempl/pep.sc b/ld/scripttempl/pep.sc
|
||||
--- a/ld/scripttempl/pep.sc 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/ld/scripttempl/pep.sc 2021-08-28 13:05:42.673576567 -0500
|
||||
@@ -127,10 +127,8 @@
|
||||
LONG (0); LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1); LONG (-1);
|
||||
KEEP (*(.dtors));
|
||||
KEEP (*(.dtor));
|
||||
diff -ur a/ld/scripttempl/pe.sc b/ld/scripttempl/pe.sc
|
||||
--- a/ld/scripttempl/pe.sc 2021-07-08 06:37:20.000000000 -0500
|
||||
+++ b/ld/scripttempl/pe.sc 2021-08-28 13:05:42.673576567 -0500
|
||||
@@ -126,10 +126,8 @@
|
||||
LONG (0);
|
||||
}
|
||||
${CONSTRUCTING+
|
||||
- /* See comment about __CTOR_LIST__ above. The same reasoning
|
||||
- applies here too. */
|
||||
- ___DTOR_LIST__ = .;
|
||||
- __DTOR_LIST__ = .;
|
||||
+ PROVIDE(___DTOR_LIST__ = .);
|
||||
+ PROVIDE(__DTOR_LIST__ = .);
|
||||
LONG (-1);
|
||||
KEEP(*(.dtors));
|
||||
KEEP(*(.dtor));
|
||||
@ -0,0 +1,13 @@
|
||||
diff --git a/Makefile b/Makefile
|
||||
index ed6e7ec60eff..c7a78e04e062 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -1300,7 +1300,7 @@ PHONY += archheaders archscripts
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/Makefile 2020-04-19 10:30:53.176029776 +0000
|
||||
+++ b/Makefile 2020-04-19 10:32:15.981722937 +0000
|
||||
@@ -1189,7 +1189,7 @@
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/Makefile 2020-04-19 10:30:53.176029776 +0000
|
||||
+++ b/Makefile 2020-04-19 10:32:15.981722937 +0000
|
||||
@@ -1189,7 +1189,7 @@
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/Makefile 2020-04-19 10:30:53.176029776 +0000
|
||||
+++ b/Makefile 2020-04-19 10:32:15.981722937 +0000
|
||||
@@ -1189,7 +1189,7 @@
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/Makefile 2020-04-19 10:30:53.176029776 +0000
|
||||
+++ b/Makefile 2020-04-19 10:32:15.981722937 +0000
|
||||
@@ -1189,7 +1189,7 @@
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/Makefile 2020-04-19 10:30:53.176029776 +0000
|
||||
+++ b/Makefile 2020-04-19 10:32:15.981722937 +0000
|
||||
@@ -1189,7 +1189,7 @@
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/Makefile 2020-04-19 10:30:53.176029776 +0000
|
||||
+++ b/Makefile 2020-04-19 10:32:15.981722937 +0000
|
||||
@@ -1189,7 +1189,7 @@
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -0,0 +1,11 @@
|
||||
--- a/Makefile 2020-04-19 10:30:53.176029776 +0000
|
||||
+++ b/Makefile 2020-04-19 10:32:15.981722937 +0000
|
||||
@@ -1189,7 +1189,7 @@
|
||||
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
||||
|
||||
PHONY += headers
|
||||
-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
+headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
@ -1,74 +0,0 @@
|
||||
#!/bin/sh -e
|
||||
|
||||
HERE=$(dirname $(readlink -f ${0}))
|
||||
|
||||
LOGS=${HERE}/../logs
|
||||
BINS=${HERE}/../output
|
||||
OBJS=${HERE}/../build
|
||||
|
||||
CSUF=cross
|
||||
NSUF=native
|
||||
|
||||
KALE="${PATH}"
|
||||
MCMT=;
|
||||
|
||||
##
|
||||
# Check whether target triple is specified.
|
||||
#
|
||||
test ${#} != 1 && printf "No target triple specified!\n" && exit 1;
|
||||
|
||||
##
|
||||
# When 'MCMTOOLS' is specified, ensure it is valid (at first glance).
|
||||
#
|
||||
if ! test -z ${MCMTOOLS}; then
|
||||
MCMT="${MCMTOOLS%/}";
|
||||
fail=0;
|
||||
test -d "${MCMT}/sys/bin" || fail=1;
|
||||
test -d "${MCMT}/host/bin" || fail=1;
|
||||
test -d "${MCMT}/musl/bin" || fail=1;
|
||||
test $fail -eq 1 && printf "Using 'MCMTOOLS=%s' is not valid.\n" "${MCMTOOLS}" && exit 1;
|
||||
fi
|
||||
|
||||
mkdir -p ${LOGS} ${BINS}
|
||||
|
||||
# CROSS BUILD INSTALL
|
||||
if ! test -z ${MCMT}; then
|
||||
export PATH="${MCMT}/sys/bin:${MCMT}/musl/bin";
|
||||
else
|
||||
export PATH="${KALE}";
|
||||
fi
|
||||
[ -d ${BINS}/${1}-${CSUF} ] || make install \
|
||||
TARGET=${1} OUTPUT=${BINS}/${1}-${CSUF} \
|
||||
2>&1 | tee ${LOGS}/${1}-${CSUF}.log
|
||||
|
||||
# CROSS SCRATCH CLEANUP
|
||||
rm -fr ${OBJS}/local/${1}
|
||||
|
||||
# CROSS PACKAGE
|
||||
[ -h ${BINS}/${1}-${CSUF}/usr ] || (cd ${BINS}/${1}-${CSUF} && ln -s . usr)
|
||||
[ -e ${BINS}/${1}-${CSUF}.tgz ] || (cd ${BINS} && tar pczf ${1}-${CSUF}.tgz ${1}-${CSUF})
|
||||
|
||||
# NATIVE BUILD INSTALL
|
||||
if ! test -z ${MCMT}; then
|
||||
export PATH="${MCMT}/sys/bin:${MCMT}/host/bin:${BINS}/${1}-${CSUF}/bin";
|
||||
else
|
||||
export PATH="${KALE}:${BINS}/${1}-${CSUF}/bin";
|
||||
fi
|
||||
if [ -d ${BINS}/${1}-${CSUF} ]; then
|
||||
[ -d ${BINS}/${1}-${NSUF} ] || make install NATIVE=1 \
|
||||
TARGET=${1} CROSS_COMPILE=${1}- OUTPUT=${BINS}/${1}-${NSUF} \
|
||||
2>&1 | tee ${LOGS}/${1}-${NSUF}.log
|
||||
fi;
|
||||
|
||||
# CROSS DIRECTORY CLEANUP (if native fails, this remains)
|
||||
rm -fr ${BINS}/${1}-${CSUF};
|
||||
|
||||
# NATIVE PACKAGE
|
||||
[ -h ${BINS}/${1}-${NSUF}/usr ] || (cd ${BINS}/${1}-${NSUF} && ln -s . usr)
|
||||
[ -e ${BINS}/${1}-${NSUF}.tgz ] || (cd ${BINS} && tar pczf ${1}-${NSUF}.tgz ${1}-${NSUF});
|
||||
|
||||
# NATIVE SCRATCH CLEANUP
|
||||
rm -fr ${OBJS}/${1}
|
||||
|
||||
# NATIVE DIRECTORY CLEANUP
|
||||
rm -fr ${BINS}/${1}-${NSUF};
|
||||
@ -1,34 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
HERE=$(dirname $(readlink -f ${0}))
|
||||
|
||||
LIST=${HERE}/triples.txt
|
||||
CFGS=${HERE}/../sources/config.sub
|
||||
|
||||
##
|
||||
# When 'MCMTOOLS' is specified, ensure it is valid (at first glance).
|
||||
#
|
||||
if ! test -z ${MCMTOOLS}; then
|
||||
MCMT="${MCMTOOLS%/}";
|
||||
fail=0;
|
||||
test -d "${MCMT}/sys/bin" || fail=1;
|
||||
test -d "${MCMT}/host/bin" || fail=1;
|
||||
test -d "${MCMT}/musl/bin" || fail=1;
|
||||
test $fail -eq 1 && printf "Using 'MCMTOOLS=%s' is not valid.\n" "${MCMTOOLS}" && exit 1;
|
||||
fi
|
||||
|
||||
export MCMTOOLS="${MCMT}";
|
||||
|
||||
##
|
||||
# WARNING: YOU MUST BE INSANE TO USE A VALUE GREATER THAN 1 HERE.
|
||||
# This means: "Run N jobs, each job with M threads" where M is 'nproc'.
|
||||
# Why? Useful for bruteforcing toolchain builds and keeping CPU busy.
|
||||
# You may destroy an SSD with too high of a value. Use a ramdisk only.
|
||||
#
|
||||
JOBS=6;
|
||||
|
||||
if ! test -z ${MCMTOOLS}; then
|
||||
export PATH="${MCMT}/sys/bin";
|
||||
fi
|
||||
make extract_all;
|
||||
grep -v ^# "${LIST}" | parallel --eta --bar --progress --plain -j${JOBS} -a - "${HERE}/build";
|
||||
@ -1,34 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
HERE=$(dirname $(readlink -f ${0}))
|
||||
|
||||
LIST=${HERE}/triples.txt
|
||||
CFGS=${HERE}/../sources/config.sub
|
||||
|
||||
##
|
||||
# When 'MCMTOOLS' is specified, ensure it is valid (at first glance).
|
||||
#
|
||||
if ! test -z ${MCMTOOLS}; then
|
||||
MCMT="${MCMTOOLS%/}";
|
||||
fail=0;
|
||||
test -d "${MCMT}/sys/bin" || fail=1;
|
||||
test -d "${MCMT}/host/bin" || fail=1;
|
||||
test -d "${MCMT}/musl/bin" || fail=1;
|
||||
test $fail -eq 1 && printf "Using 'MCMTOOLS=%s' is not valid.\n" "${MCMTOOLS}" && exit 1;
|
||||
fi
|
||||
|
||||
export MCMTOOLS="${MCMT}";
|
||||
|
||||
##
|
||||
# WARNING: YOU MUST BE INSANE TO USE A VALUE GREATER THAN 1 HERE.
|
||||
# This means: "Run N jobs, each job with M threads" where M is 'nproc'.
|
||||
# Why? Useful for bruteforcing toolchain builds and keeping CPU busy.
|
||||
# You may destroy an SSD with too high of a value. Use a ramdisk only.
|
||||
#
|
||||
JOBS=6;
|
||||
|
||||
if ! test -z ${MCMTOOLS}; then
|
||||
export PATH="${MCMT}/sys/bin";
|
||||
fi
|
||||
make extract_all;
|
||||
grep -v ^# "${LIST}" | parallel --eta --bar --progress --plain -j${JOBS} -a - "${HERE}/buildcross";
|
||||
@ -1,28 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
# https://stackoverflow.com/a/1116890
|
||||
s=$(pwd)
|
||||
_=$0
|
||||
cd `dirname $0`
|
||||
_=`basename $_`
|
||||
#while [ -L "$_" ]; do
|
||||
# _=`readlink $_`;
|
||||
# cd `dirname $_`;
|
||||
# _=`basename $_`;
|
||||
#done
|
||||
HERE=`pwd -P`/$_
|
||||
cd $s
|
||||
|
||||
LIST=${HERE}/triples.txt
|
||||
CFGS=${HERE}/../sources/config.sub
|
||||
|
||||
##
|
||||
# WARNING: YOU MUST BE INSANE TO USE A VALUE GREATER THAN 1 HERE.
|
||||
# This means: "Run N jobs, each job with M threads" where M is 'nproc'.
|
||||
# Why? Useful for bruteforcing toolchain builds and keeping CPU busy.
|
||||
# You may destroy an SSD with too high of a value. Use a ramdisk only.
|
||||
#
|
||||
JOBS=2;
|
||||
|
||||
make extract_all;
|
||||
grep -v ^# "${LIST}" | parallel --eta --bar --progress --plain -j${JOBS} -a - ${HERE}/buildmac;
|
||||
@ -1,52 +0,0 @@
|
||||
#!/bin/sh -e
|
||||
|
||||
HERE=$(dirname $(readlink -f ${0}))
|
||||
|
||||
LOGS=${HERE}/../logs
|
||||
BINS=${HERE}/../output
|
||||
OBJS=${HERE}/../build
|
||||
|
||||
CSUF=cross
|
||||
NSUF=native
|
||||
|
||||
KALE="${PATH}"
|
||||
MCMT=;
|
||||
|
||||
##
|
||||
# Check whether target triple is specified.
|
||||
#
|
||||
test ${#} != 1 && printf "No target triple specified!\n" && exit 1;
|
||||
|
||||
##
|
||||
# When 'MCMTOOLS' is specified, ensure it is valid (at first glance).
|
||||
#
|
||||
if ! test -z ${MCMTOOLS}; then
|
||||
MCMT="${MCMTOOLS%/}";
|
||||
fail=0;
|
||||
test -d "${MCMT}/sys/bin" || fail=1;
|
||||
test -d "${MCMT}/host/bin" || fail=1;
|
||||
test -d "${MCMT}/musl/bin" || fail=1;
|
||||
test $fail -eq 1 && printf "Using 'MCMTOOLS=%s' is not valid.\n" "${MCMTOOLS}" && exit 1;
|
||||
fi
|
||||
|
||||
mkdir -p ${LOGS} ${BINS}
|
||||
|
||||
# CROSS BUILD INSTALL
|
||||
if ! test -z ${MCMT}; then
|
||||
export PATH="${MCMT}/sys/bin:${MCMT}/musl/bin";
|
||||
else
|
||||
export PATH="${KALE}";
|
||||
fi
|
||||
[ -d ${BINS}/${1}-${CSUF} ] || make install \
|
||||
TARGET=${1} OUTPUT=${BINS}/${1}-${CSUF} \
|
||||
2>&1 | tee ${LOGS}/${1}-${CSUF}.log
|
||||
|
||||
# CROSS SCRATCH CLEANUP
|
||||
rm -fr ${OBJS}/local/${1}
|
||||
|
||||
# CROSS PACKAGE
|
||||
[ -h ${BINS}/${1}-${CSUF}/usr ] || (cd ${BINS}/${1}-${CSUF} && ln -s . usr)
|
||||
[ -e ${BINS}/${1}-${CSUF}.tgz ] || (cd ${BINS} && tar pczf ${1}-${CSUF}.tgz ${1}-${CSUF})
|
||||
|
||||
# CROSS DIRECTORY CLEANUP (if native fails, this remains)
|
||||
rm -fr ${BINS}/${1}-${CSUF};
|
||||
@ -1,39 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
# https://stackoverflow.com/a/1116890
|
||||
s=$(pwd)
|
||||
_=$0
|
||||
cd `dirname $0`
|
||||
_=`basename $_`
|
||||
#while [ -L "$_" ]; do
|
||||
# _=`readlink $_`;
|
||||
# cd `dirname $_`;
|
||||
# _=`basename $_`;
|
||||
#done
|
||||
HERE=`pwd -P`/$_
|
||||
cd $s
|
||||
|
||||
LOGS=${HERE}/../logs
|
||||
BINS=${HERE}/../output
|
||||
OBJS=${HERE}/../build
|
||||
|
||||
CSUF=cross
|
||||
|
||||
KALE="${PATH}"
|
||||
|
||||
mkdir -p ${LOGS} ${BINS}
|
||||
|
||||
# CROSS BUILD
|
||||
[ -d ${BINS}/${1}-${CSUF} ] || make install \
|
||||
TARGET=${1} OUTPUT=${BINS}/${1}-${CSUF} \
|
||||
2>&1 | tee ${LOGS}/${1}-${CSUF}.log
|
||||
|
||||
# CROSS PACKAGE
|
||||
[ -h ${BINS}/${1}-${CSUF}/usr ] || (cd ${BINS}/${1}-${CSUF} && ln -s . usr)
|
||||
[ -e ${BINS}/${1}-${CSUF}.tgz ] || (cd ${BINS} && tar pczf ${1}-${CSUF}.tgz ${1}-${CSUF})
|
||||
|
||||
# CROSS CLEANUP
|
||||
rm -fr ${OBJS}/local/${1}
|
||||
|
||||
# DIRECTORY CLEANUP
|
||||
rm -fr ${BINS}/${1}-${CSUF};
|
||||
260
scripts/macsimum
260
scripts/macsimum
@ -1,260 +0,0 @@
|
||||
#!/bin/sh -e
|
||||
|
||||
#===============================================================
|
||||
# Filename : macsimum
|
||||
# Purpose : Builds Mac-to-Linux cross-compiler toolchains.
|
||||
# Authors : Zach van Rijn <me@zv.io>
|
||||
# License : MIT
|
||||
# Revision : 20200303
|
||||
#===============================================================
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# README
|
||||
#
|
||||
# overview
|
||||
# --------
|
||||
#
|
||||
# This script builds "musl-cross-make" cross-compiler toolchains
|
||||
# that are hosted on macOS and target Linux. For example, your
|
||||
# Macintosh machine can use up-to-date versions of GCC to build
|
||||
# code (C, C++, Fortran) for your MIPS router. The libc used is
|
||||
# called 'musl': https://www.musl-libc.org/faq.html
|
||||
#
|
||||
# Others have tried and failed to deliver what you're able to do
|
||||
# with this tiny script.
|
||||
#
|
||||
# What does this look like? Modern GCC that does:
|
||||
#
|
||||
# * macOS --> ARM, Motorola 68000, MIPS, OpenRISC, PowerPC,
|
||||
# RISC-V, S/390, SuperH, x86-based, more?
|
||||
#
|
||||
# The goal, of course, is to achieve parity with musl.cc's Linux
|
||||
# offerings. A link to pre-built macOS binaries is now public,
|
||||
# and this is the script to reproduce them. https://mac.musl.cc/
|
||||
#
|
||||
#
|
||||
# requirements
|
||||
# ------------
|
||||
#
|
||||
# Basically, you need XCode Command Line Tools. I don't know any
|
||||
# specific version requirements, but if you encounter problems I
|
||||
# would appreciate a heads up.
|
||||
#
|
||||
# This document may be useful: https://git.zv.io/snippets/34/raw
|
||||
#
|
||||
# You'll also need a working internet connection.
|
||||
#
|
||||
# A previous version of this script relied on Homebrew for some
|
||||
# of the utilities that we're using. This, contrary to intent,
|
||||
# created a Homebrew dependency. No longer! Build products are
|
||||
# now fully portable (across compatible macOS / OS X versions).
|
||||
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Dependency versions (for bootstrap compiler and tooling)
|
||||
|
||||
V_SED=4.7 ;
|
||||
V_PAT=2.7.6 ;
|
||||
V_GMP=6.1.2 ;
|
||||
V_MPF=4.0.2 ;
|
||||
V_MPC=1.1.0 ;
|
||||
V_ISL=0.21 ;
|
||||
V_GCC=9.2.0 ;
|
||||
V_BUT=2.34 ;
|
||||
|
||||
V_GM4=1.4.18;
|
||||
V_BIS=3.4.2 ;
|
||||
V_FLX=2.6.4 ;
|
||||
V_CUT=8.31 ;
|
||||
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Production compiler configuration data (or use heredoc)
|
||||
|
||||
tool=musl-cross-make; # musl-cross-make repository
|
||||
conf=$(curl -s https://conf.musl.cc/mac_20200229_9-2-1.txt);
|
||||
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Dependency mirrors
|
||||
|
||||
M_GNU=https://ftp.gnu.org/gnu;
|
||||
M_ISL=http://isl.gforge.inria.fr;
|
||||
|
||||
M_FLX=https://github.com/westes/flex/releases/download;
|
||||
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Build configuration
|
||||
|
||||
##
|
||||
# It is possible to build all library and utility dependencies
|
||||
# for the building of musl-cross-make production toolchains on a
|
||||
# RAM disk. This may improve performance on systems with slow
|
||||
# disks, and requires approximately 3GB of space. 4GB is safe:
|
||||
#
|
||||
# $ diskutil erasevolume HFS+ "RAMDISK" \
|
||||
# `hdiutil attach -nomount ram://$((2048 * 1024 * 4))`
|
||||
#
|
||||
# The '4' in the above example represents gigabytes.
|
||||
|
||||
rdsk=/Volumes/RAMDISK; # dependency build prefix
|
||||
|
||||
##
|
||||
# When the production toolchains are built, a significant bit of
|
||||
# disk space is required. Do not attempt to build them in RAM if
|
||||
# you are not on a server server with several dozen gigabytes of
|
||||
# RAM and the assurance that your system won't crash :)
|
||||
|
||||
bdsk=/tmp; # production build prefix
|
||||
|
||||
##
|
||||
# This directory will contain dependency build trees. It can be
|
||||
# deleted after the toolchains are built.
|
||||
|
||||
bdir=${rdsk}/tmp; # scratch directory location
|
||||
|
||||
##
|
||||
# Within each dependency build tree, we want to perform an out-
|
||||
# of-tree build. This is the (arbitrary) name of that directory.
|
||||
|
||||
tdir=x; # out-of-tree directory name
|
||||
|
||||
##
|
||||
# This directory will contain the dependency libraries and tools
|
||||
# and can also be deleted after the toolchains are built, but it
|
||||
# may be useful to maintain this directory for future builds.
|
||||
|
||||
sdir=${rdsk}/sys; # system installation directory
|
||||
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Supporting routines
|
||||
|
||||
# prep <URL> <TARFLAG> <STRIP> [<CONFIG> ...]
|
||||
prep ()
|
||||
{
|
||||
_tar="${1}"; shift;
|
||||
_str="${1}"; shift;
|
||||
_url="${1}"; shift;
|
||||
_cnf="${@}";
|
||||
|
||||
base=$(basename ${_url}); # name of file being downloaded
|
||||
name=${base%-*}; # name of project w/o version
|
||||
|
||||
[ ! -f "${sdir}/._${base}" ] || return 0;
|
||||
|
||||
rm -fr "${bdir}/${name}";
|
||||
mkdir -p "${bdir}/${name}/${tdir}";
|
||||
|
||||
cd "${bdir}/${name}";
|
||||
curl -sL ${_url} \
|
||||
| tar --strip-components=${_str} -x${_tar}f -;
|
||||
|
||||
cd "${tdir}";
|
||||
|
||||
( # subshell for isolation
|
||||
export PATH="${sdir}/bin:$PATH";
|
||||
|
||||
export CPPFLAGS="-I${sdir}/include";
|
||||
export CFLAGS="";
|
||||
export CXXFLAGS="";
|
||||
export LDFLAGS="-L${sdir}/lib";
|
||||
|
||||
../configure --prefix="${sdir}" ${_cnf};
|
||||
make && make install;
|
||||
|
||||
touch "${sdir}/._${base}";
|
||||
)
|
||||
}
|
||||
|
||||
# (no args) Builds production toolchains for mac.musl.cc
|
||||
musl ()
|
||||
{
|
||||
cd "${bdsk}";
|
||||
|
||||
if [ ! -d "${tool}" ]; then
|
||||
git clone https://git.zv.io/toolchains/${tool}.git;
|
||||
fi
|
||||
|
||||
cd ${tool};
|
||||
|
||||
printf > config.mak "%s\n" "${conf}";
|
||||
|
||||
PATH="${sdir}/bin:$PATH" ./scripts/buildmac;
|
||||
}
|
||||
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Stage 1: Bootstrap compiler
|
||||
|
||||
prep j 1 ${M_GNU}/sed/sed-${V_SED}.tar.xz \
|
||||
;
|
||||
|
||||
prep j 1 ${M_GNU}/patch/patch-${V_PAT}.tar.xz \
|
||||
;
|
||||
|
||||
prep j 1 ${M_GNU}/m4/m4-${V_GM4}.tar.xz \
|
||||
;
|
||||
|
||||
prep j 1 ${M_GNU}/bison/bison-${V_BIS}.tar.xz \
|
||||
;
|
||||
|
||||
prep z 1 ${M_FLX}/v${V_FLX}/flex-${V_FLX}.tar.gz \
|
||||
--disable-shared \
|
||||
--enable-static \
|
||||
;
|
||||
|
||||
prep j 1 ${M_GNU}/gmp/gmp-${V_GMP}.tar.xz \
|
||||
--disable-shared \
|
||||
--enable-static \
|
||||
--enable-cxx \
|
||||
;
|
||||
|
||||
prep j 1 ${M_GNU}/mpfr/mpfr-${V_MPF}.tar.xz \
|
||||
--disable-shared \
|
||||
--enable-static \
|
||||
--with-gmp="${sdir}" \
|
||||
;
|
||||
|
||||
prep z 1 ${M_GNU}/mpc/mpc-${V_MPC}.tar.gz \
|
||||
--disable-shared \
|
||||
--enable-static \
|
||||
--with-gmp="${sdir}" \
|
||||
;
|
||||
|
||||
prep j 1 ${M_ISL}/isl-${V_ISL}.tar.xz \
|
||||
--disable-shared \
|
||||
--enable-static \
|
||||
--with-gmp-prefix="${sdir}" \
|
||||
;
|
||||
|
||||
prep j 1 ${M_GNU}/coreutils/coreutils-${V_CUT}.tar.xz \
|
||||
--disable-shared \
|
||||
--enable-static \
|
||||
FORCE_UNSAFE_CONFIGURE=1 \
|
||||
;
|
||||
|
||||
prep j 1 ${M_GNU}/gcc/gcc-${V_GCC}/gcc-${V_GCC}.tar.xz \
|
||||
--enable-languages=c,c++ \
|
||||
--with-gmp="${sdir}" \
|
||||
--with-mpfr="${sdir}" \
|
||||
--with-mpc="${sdir}" \
|
||||
--with-isl="${sdir}" \
|
||||
--enable-multilib \
|
||||
--disable-bootstrap \
|
||||
;
|
||||
|
||||
if false; then
|
||||
prep j 1 ${M_GNU}/binutils/binutils-${V_BUT}.tar.xz \
|
||||
--disable-shared \
|
||||
--enable-static \
|
||||
--disable-multilib \
|
||||
;
|
||||
fi
|
||||
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Stage 2: Production toolchains
|
||||
|
||||
musl;
|
||||
@ -1,63 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
LIST=$(dirname $(which ${0}))/triples.txt
|
||||
LOGS=$(dirname $(which ${0}))/../logs
|
||||
BINS=$(dirname $(which ${0}))/../output
|
||||
|
||||
KALE="${PATH}"
|
||||
OVER=""
|
||||
|
||||
optics()
|
||||
{
|
||||
# flags
|
||||
case ${1} in
|
||||
*microblaze*)
|
||||
# ICE in GCC; temporarily disable gfortran support.
|
||||
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87438
|
||||
OVER="GCC_CONFIG=\"--enable-languages=c,c++\""
|
||||
;;
|
||||
*)
|
||||
OVER=""
|
||||
;;
|
||||
esac
|
||||
}
|
||||
|
||||
# host toolchains (still static)
|
||||
mkdir -p ${LOGS} ${BINS}
|
||||
for s in $(cat ${LIST} | grep -v "#"); do
|
||||
# flags
|
||||
optics ${s}
|
||||
|
||||
# host
|
||||
[ -d ${BINS}/${s}-host ] || make ${OVER} install \
|
||||
TARGET=${s} \
|
||||
OUTPUT=${BINS}/${s}-host \
|
||||
2>&1 | tee ${LOGS}/${s}-host.log
|
||||
done;
|
||||
|
||||
# enter the matrix
|
||||
for s in $(cat ${LIST} | grep -v "#"); do
|
||||
#make -C $(dirname $(which ${0}))/../ clean
|
||||
mkdir -p ${BINS}/matrix/${s}
|
||||
for t in $(cat ${LIST} | grep -v "#"); do
|
||||
# flags
|
||||
optics ${t}
|
||||
|
||||
# matrix
|
||||
if [ -d ${BINS}/${s}-host ]; then
|
||||
export PATH="${KALE}:${BINS}/${s}-host/bin"
|
||||
[ -d ${BINS}/matrix/${s}/${t} ] || make ${OVER} install \
|
||||
CROSS_COMPILE=${s}- \
|
||||
HOST=${s} \
|
||||
TARGET=${t} \
|
||||
OUTPUT=${BINS}/matrix/${s}/${t} \
|
||||
2>&1 | tee ${LOGS}/${s}-${t}.log
|
||||
export PATH="${KALE}"
|
||||
fi;
|
||||
done;
|
||||
done;
|
||||
|
||||
#cd ${BINS}
|
||||
#for t in $(find . -mindepth 1 -maxdepth 1 -type d); do
|
||||
# [ -e ${t}.tgz ] || tar pczf ${t}.tgz ${t};
|
||||
#done
|
||||
361
scripts/sinner
361
scripts/sinner
@ -1,361 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#===============================================================
|
||||
# Filename : scripts/sinner
|
||||
# Purpose : Builds Linux-to-Windows cross-compiler toolchains.
|
||||
# Authors : Zach van Rijn <me@zv.io>
|
||||
# License : MIT
|
||||
# Revision : 20190531
|
||||
#===============================================================
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# README
|
||||
#
|
||||
# overview
|
||||
# --------
|
||||
#
|
||||
# This script builds "musl-cross-make" cross-compiler toolchains
|
||||
# that are hosted on Linux and target Windows. For example, your
|
||||
# MIPS router can use up-to-date versions of GCC to build code
|
||||
# (C, C++, Fortran) for your Windows XP machine. The libc used
|
||||
# is called 'musl': https://www.musl-libc.org/faq.html
|
||||
#
|
||||
# Others have tried and failed to deliver what you're able to do
|
||||
# with this tiny script. Additions to this list are welcome:
|
||||
#
|
||||
# What does this look like? Modern GCC that does:
|
||||
#
|
||||
# * Linux on ARM, Motorola 68000, MIPS, OpenRISC, PowerPC,
|
||||
# RISC-V, S/390, SuperH, x86-based, more?
|
||||
#
|
||||
# --> Windows XP to 10, and possibly older.
|
||||
#
|
||||
# The goal, of course, is to achieve parity with musl.cc's Linux
|
||||
# offerings. This is the script to build the binaries located at
|
||||
# https://more.musl.cc/YOUR-HOST-ARCHITECTURE/*-w64-mingw32.zip
|
||||
#
|
||||
#
|
||||
# build platforms
|
||||
# ---------------
|
||||
#
|
||||
# You need Linux to build these, and an architecture that runs a
|
||||
# toolchain from musl.cc.
|
||||
#
|
||||
#
|
||||
# requirements
|
||||
# ------------
|
||||
#
|
||||
# Consider running this script inside of an isolated environment
|
||||
# such as a container or virtual machine. While not required, we
|
||||
# do not recommend running any foreign scripts or binaries in an
|
||||
# important environment. You'll need the following packages:
|
||||
#
|
||||
# * cmake
|
||||
# * curl
|
||||
# * git
|
||||
# * make
|
||||
# * patch (GNU)
|
||||
# * tar
|
||||
# * xz
|
||||
# * zip
|
||||
#
|
||||
# e.g., apk add cmake curl git make patch rsync tar xz zip
|
||||
#
|
||||
#
|
||||
# other notes
|
||||
# -----------
|
||||
#
|
||||
# * A prior version of this script ('prepare') relies on Linux
|
||||
# 'binfmt_misc' and QEMU to emulate certain build byproducts
|
||||
# and requires root privileges to install (but not use) that
|
||||
# setup. This version cross-compiles the toolchains purely.
|
||||
#
|
||||
# * This script uses the 'mingw-cross-make' flavor maintained
|
||||
# at https://git.zv.io/toolchains/mingw-cross-make to build
|
||||
# MinGW toolchains. Issues should be addressed there.
|
||||
#
|
||||
#
|
||||
# usage
|
||||
# -----
|
||||
#
|
||||
# $ ./scripts/sinner [TRIPLE ...]
|
||||
#
|
||||
# $ ./scripts/sinner i686-w64-mingw32 x86_64-w64-mingw32
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Configuration.
|
||||
|
||||
## Component Versions
|
||||
#
|
||||
# These options are self explanatory, but *must* correspond to a
|
||||
# supported version within the "musl-cross-make" repository. One
|
||||
# other factor to consider is that kernel headers and musl libc
|
||||
# will be harvested from a "donor" toolchain; these versions do
|
||||
# not necessarily correspond to what is built here (yet, TODO).
|
||||
#
|
||||
GCC_VER=9.1.0
|
||||
BINUTILS_VER=2.32
|
||||
MUSL_VER=git-a60b9e06861e56c0810bae0249b421e1758d281a
|
||||
GMP_VER=6.1.2
|
||||
MPC_VER=1.1.0
|
||||
MPFR_VER=4.0.2
|
||||
MINGW_VER=git-3e6c10aeba81c589a7b2ed1e7daee4d4d75b646e
|
||||
|
||||
## Directories
|
||||
#
|
||||
# By default, all toolchains that can be built, are built. This
|
||||
# requires a significant amount of disk space. Please ensure you
|
||||
# have at least 50GB of free disk space in these directories:
|
||||
#
|
||||
base="${HOME}/sinner_src" # base source directory
|
||||
huge="${HOME}/sinner_bld" # base build directory
|
||||
logs="${HOME}/sinner_log" # suite build log directory
|
||||
zips="${HOME}/sinner_bin" # completed toolchains go here
|
||||
|
||||
## Toolchain Mirror
|
||||
#
|
||||
# If you have access to an x86_64 Linux machine, or one that has
|
||||
# an x86_64 QEMU user-mode emulator registered in 'binfmt_misc',
|
||||
# you will always be using the latest available software.
|
||||
#
|
||||
musl=https://more.musl.cc # more.musl.cc or mirror
|
||||
|
||||
## Toolchain Naming Conventions
|
||||
#
|
||||
# The musl.cc toolchains follow a simple naming convention: all
|
||||
# cross compilers are suffixed with '-cross', native '-native'.
|
||||
# If you're using a different mirror or convention, set it here.
|
||||
#
|
||||
csuf=-cross # cross suffix
|
||||
nsuf=-native # native suffix
|
||||
|
||||
## Toolchain Tuples
|
||||
#
|
||||
# Values can be found at 'https://more.musl.cc/' where the $user
|
||||
# variable corresponds to your build platform, and $host to your
|
||||
# intended Linux development environment. Note that unless the
|
||||
# website says otherwise, only the 'x86_64-linux-musl' toolchain
|
||||
# directory is up-to-date. If you can't find what you're looking
|
||||
# for you must build a MinGW-w64 suitable toolchain from source.
|
||||
#
|
||||
user=x86_64-linux-musl # platform that builds suite
|
||||
|
||||
## Build Environment
|
||||
#
|
||||
# This variable is extended during the toolchain download step.
|
||||
#
|
||||
kale="${base}/${user}${csuf}/bin";
|
||||
|
||||
## Repositories
|
||||
#
|
||||
# The build infrastructure used is called "musl-cross-make" and
|
||||
# is upstream https://github.com/richfelker/musl-cross-make, but
|
||||
# this version is incompatible with the current script. It's out
|
||||
# of date, too, so please leave the default unless you fork it.
|
||||
#
|
||||
name=musl-cross-make
|
||||
repo=https://git.zv.io/toolchains/${name}
|
||||
brch=musl-git # branch name (no assumptions!)
|
||||
|
||||
sinn=mingw-cross-make
|
||||
sinr=https://git.zv.io/toolchains/${sinn}
|
||||
sinb=mingw
|
||||
|
||||
## Suite Targets
|
||||
#
|
||||
# Now that RISC-V patches are (unofficially) merged into musl, a
|
||||
# single text file with target tuples (which comprise the suite)
|
||||
# may now be used. Modify this with e.g. a pastebin link if you
|
||||
# wish to use a different list (this one is self-updating).
|
||||
#
|
||||
list=${repo}/raw/${brch}/scripts/triples.txt
|
||||
filt=tuples.txt # filename of saved tuples list
|
||||
|
||||
## Suite Configuration
|
||||
#
|
||||
# To facilitate users' needs in customizing the toolchain suite,
|
||||
# a configuration file is embedded below. These settings *must*
|
||||
# be supported by the repository specified above.
|
||||
#
|
||||
# Note: items that are prefixed/suffixed with double underscores
|
||||
# are automatically populated later. Do not modify them here!
|
||||
#
|
||||
conf=$(cat <<'EOF'
|
||||
STAT = -static --static
|
||||
FLAG = -g0 -O2 -fno-align-functions -fno-align-jumps -fno-align-loops -fno-align-labels
|
||||
|
||||
COMMON_CONFIG += CC="$(HOST)-gcc ${STAT}" CXX="$(HOST)-g++ ${STAT}" FC="$(HOST)-gfortran -${STAT}"
|
||||
COMMON_CONFIG += CFLAGS="${FLAG}" CXXFLAGS="${FLAG}" FFLAGS="${FLAG}" LDFLAGS="-s ${STAT}"
|
||||
COMMON_CONFIG += --disable-nls --disable-bootstrap --build=__USER__ --host=__HOST__ --target=__TARG__
|
||||
|
||||
GCC_CONFIG += --enable-threads=__THREADS__
|
||||
OVERRIDE = --enable-libquadmath --enable-libquadmath-support
|
||||
|
||||
GCC_VER = __GCC_VER__
|
||||
BINUTILS_VER = __BINUTILS_VER__
|
||||
MUSL_VER = __MUSL_VER__
|
||||
GMP_VER = __GMP_VER__
|
||||
MPC_VER = __MPC_VER__
|
||||
MPFR_VER = __MPFR_VER__
|
||||
MINGW_VER = __MINGW_VER__
|
||||
LINUX_VER =
|
||||
EOF
|
||||
);
|
||||
|
||||
## Thread Configuration
|
||||
#
|
||||
# By popular demand, both Win32 and POSIX thread models will are
|
||||
# supported. Edit this variable if you don't wish to build both.
|
||||
#
|
||||
tmod="posix" # default: "win32 posix"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Subroutines.
|
||||
|
||||
# Download preliminary toolchains.
|
||||
#
|
||||
get_tool ()
|
||||
{
|
||||
mkdir -p "${base}";
|
||||
|
||||
# build
|
||||
if [ ! -d "${base}/${user}${csuf}" ]; then
|
||||
curl ${musl}/${user}/${user}${csuf}.tgz \
|
||||
| tar 2>/dev/null -C "${base}" -xzf -;
|
||||
fi
|
||||
}
|
||||
|
||||
# Clone a suitable "musl-cross-make" repository.
|
||||
#
|
||||
get_repo ()
|
||||
{
|
||||
[ -d "${base}" ] || exit 1;
|
||||
[ ! -d "${base}/${sinn}" ] || return;
|
||||
git clone ${sinr} "${base}/${sinn}";
|
||||
}
|
||||
|
||||
# Overwrite any existing configuration (config.mak) template.
|
||||
#
|
||||
get_conf ()
|
||||
{
|
||||
[ -d "${base}/${sinn}" ] || exit 1;
|
||||
printf > "${base}/${sinn}/config.mak" "%s\n" \
|
||||
"${conf}";
|
||||
}
|
||||
|
||||
# Fetch an up-to-date list of possible target tuples. Allow the
|
||||
# user to edit this list, if the line is uncommented, before DL.
|
||||
#
|
||||
get_list ()
|
||||
{
|
||||
[ ! -f "${base}/${filt}" ] || return;
|
||||
curl -o "${base}/${filt}" ${list};
|
||||
sed -i "${base}/${filt}" -e '/mingw/d';
|
||||
nano "${base}/${filt}";
|
||||
}
|
||||
|
||||
# Download all necessary target toolchains.
|
||||
#
|
||||
get_targ ()
|
||||
{
|
||||
# targets (if different from build)
|
||||
cat "${base}/${filt}" | grep -v "#" | while read k; do
|
||||
if [ ! -d "${base}/${k}${csuf}" ]; then
|
||||
curl ${musl}/${user}/${k}${csuf}.tgz \
|
||||
| tar 2>/dev/null -C "${base}" -xzf -;
|
||||
fi
|
||||
done;
|
||||
}
|
||||
|
||||
# Build the compiler suite. Note: the '-ik' in 'make' is used to
|
||||
# ignore an error:
|
||||
#
|
||||
# The directory that should contain system headers does not
|
||||
# exist: //mingw/include
|
||||
#
|
||||
# We use 'make clean' to ensure that the updated configuration
|
||||
# takes full effect (relevant to thread model settings).
|
||||
#
|
||||
run_make ()
|
||||
{
|
||||
cat "${base}/${filt}" | grep -v "#" | while read k; do
|
||||
for tget in ${@}; do # command-line argument list
|
||||
for t in ${tmod}; do # thread model list
|
||||
|
||||
mkdir -p "${huge}/${k}";
|
||||
mkdir -p "${logs}/${k}";
|
||||
|
||||
get_conf; sed -i "${base}/${sinn}/config.mak" \
|
||||
-e "s@__USER__@${user}@" \
|
||||
-e "s@__HOST__@${k}@" \
|
||||
-e "s@__TARG__@${tget}@" \
|
||||
\
|
||||
-e "s@__GCC_VER__@${GCC_VER}@" \
|
||||
-e "s@__BINUTILS_VER__@${BINUTILS_VER}@" \
|
||||
-e "s@__MUSL_VER__@${MUSL_VER}@" \
|
||||
-e "s@__GMP_VER__@${GMP_VER}@" \
|
||||
-e "s@__MPC_VER__@${MPC_VER}@" \
|
||||
-e "s@__MPFR_VER__@${MPFR_VER}@" \
|
||||
-e "s@__MINGW_VER__@${MINGW_VER}@" \
|
||||
\
|
||||
-e "s@__THREADS__@${t}@";
|
||||
|
||||
if [ ! -d "${huge}/${k}/${tget}${csuf}-${t}" ]; then
|
||||
PATH="${kale}:${base}/${k}${csuf}/bin:${base}/${tget}${csuf}/bin:${PATH}" \
|
||||
\
|
||||
CC="${k}-gcc" \
|
||||
CXX="${k}-g++" \
|
||||
RANLIB="${k}-ranlib" \
|
||||
\
|
||||
CC_FOR_BUILD="${user}-gcc" \
|
||||
CXX_FOR_BUILD="${user}-g++" \
|
||||
RANLIB_FOR_BUILD="${user}-ranlib" \
|
||||
\
|
||||
make -ik -C "${base}/${sinn}" -O clean install \
|
||||
HOST=${k} \
|
||||
TARGET=${tget} \
|
||||
OUTPUT="${huge}/${k}/${tget}${csuf}-${t}" \
|
||||
2>&1 | tee \
|
||||
"${logs}/${k}/${tget}${csuf}-${t}.log";
|
||||
fi
|
||||
|
||||
done; # thread model list
|
||||
done; # command-line argument list
|
||||
done; # source list (hosts)
|
||||
}
|
||||
|
||||
# Pack the toolchains into tgz files. They're ready for distro.
|
||||
#
|
||||
run_pack ()
|
||||
{
|
||||
cat "${base}/${filt}" | grep -v "#" | while read k; do
|
||||
for tget in ${@}; do # command-line argument list
|
||||
for t in ${tmod}; do # thread model list
|
||||
|
||||
mkdir -p "${zips}/${k}";
|
||||
|
||||
if [ ! -e "${zips}/${k}/${tget}${csuf}-${t}.tgz" ]; then
|
||||
(
|
||||
cd "${huge}/${k}";
|
||||
tar -pczf "${zips}/${k}/${tget}${csuf}-${t}.tgz" \
|
||||
${tget}${csuf}-${t};
|
||||
)
|
||||
fi
|
||||
|
||||
done; # thread model list
|
||||
done; # command-line argument list
|
||||
done; # source list (hosts)
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Driver.
|
||||
|
||||
get_tool; # Download initial toolchains.
|
||||
get_repo; # Clone "musl-cross-make" repo.
|
||||
get_conf; # Write toolchain configuration.
|
||||
get_list; # Generate list of targets.
|
||||
get_targ; # Fetch "donor" toolchains.
|
||||
|
||||
run_make ${@}; # Build specified toolchains.
|
||||
run_pack ${@}; # Pack output for distribution.
|
||||
|
||||
387
scripts/winner
387
scripts/winner
@ -1,387 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#===============================================================
|
||||
# Filename : scripts/winner
|
||||
# Purpose : Builds Windows-to-Linux cross-compiler toolchains.
|
||||
# Authors : Zach van Rijn <me@zv.io>
|
||||
# License : MIT
|
||||
# Revision : 20200303
|
||||
#===============================================================
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# README
|
||||
#
|
||||
# overview
|
||||
# --------
|
||||
#
|
||||
# This script builds "musl-cross-make" cross-compiler toolchains
|
||||
# that are hosted on Windows and target Linux. For example, your
|
||||
# Windows XP machine can use up-to-date versions of GCC to build
|
||||
# code (C, C++, Fortran) for your MIPS router. The libc used is
|
||||
# called 'musl': https://www.musl-libc.org/faq.html
|
||||
#
|
||||
# Others have tried and failed to deliver what you're able to do
|
||||
# with this tiny script. Additions to this list are welcome:
|
||||
#
|
||||
# * https://gnutoolchains.com/download/
|
||||
# * (um?)
|
||||
#
|
||||
# What does this look like? Modern GCC that does:
|
||||
#
|
||||
# * Win32 --> ARM, Motorola 68000, MIPS, OpenRISC, PowerPC,
|
||||
# RISC-V, S/390, SuperH, x86-based, more?
|
||||
#
|
||||
# The goal, of course, is to achieve parity with musl.cc's Linux
|
||||
# offerings. A link to pre-built Windows binaries is now public,
|
||||
# and this is the script to reproduce them. https://win.musl.cc/
|
||||
#
|
||||
#
|
||||
# build platforms
|
||||
# ---------------
|
||||
#
|
||||
# In absolute theory, one can build this toolchain suite using a
|
||||
# "native" toolchain from 'musl.cc' suitable for your platform,
|
||||
# to build a MinGW-w64 cross-compiler (hosted on your platform,
|
||||
# targeting i686- or x86_64- Windows), then use that toolchain
|
||||
# to build the suite. Some may exist here: https://more.musl.cc/
|
||||
#
|
||||
# In practice, you just need 'i686-w64-mingw32-cross' for 32-bit
|
||||
# or 'x86_64-w64-mingw32-cross' for 64-bit that runs on your own
|
||||
# Linux (or Windows, with Cygwin or MSYS2) system.
|
||||
#
|
||||
#
|
||||
# requirements
|
||||
# ------------
|
||||
#
|
||||
# Consider running this script inside of an isolated environment
|
||||
# such as a container or virtual machine. While not required, we
|
||||
# do not recommend running any foreign scripts or binaries in an
|
||||
# important environment. You'll need the following packages:
|
||||
#
|
||||
# * cmake
|
||||
# * curl
|
||||
# * git
|
||||
# * make
|
||||
# * patch (GNU)
|
||||
# * rsync
|
||||
# * tar
|
||||
# * xz
|
||||
# * zip
|
||||
#
|
||||
# e.g., apk add cmake curl git make patch rsync tar xz zip
|
||||
#
|
||||
# You'll also need an internet connection (or manually do so) to
|
||||
# obtain corresponding "donor" toolchains from musl.cc; what we
|
||||
# are doing is pulling musl and the Linux kernel headers from an
|
||||
# existing toolchain, rather than fuss with getting them to play
|
||||
# nicely with the "Canadian" cross infrastructure.
|
||||
#
|
||||
#
|
||||
# other notes
|
||||
# -----------
|
||||
#
|
||||
# * Toolchains cannot be built with kernel headers; these are
|
||||
# copied into the output directory after the initial build.
|
||||
# Kernel version is that of donor toolchain.
|
||||
#
|
||||
# * Toolchains cannot be built with the musl library; this is
|
||||
# copied into the output directory after the initial build.
|
||||
# musl version is that of donor toolchain, but may be flaky.
|
||||
#
|
||||
# * If you do not uncomment the 'nano' line, you will build a
|
||||
# large number of toolchains. This requires an exceptional
|
||||
# amount of disk space and time. This is what I use it for.
|
||||
#
|
||||
#
|
||||
# to-do
|
||||
# -----
|
||||
#
|
||||
# * Fix underlying issue causing kernel headers and musl to be
|
||||
# not built or installed correctly.
|
||||
#
|
||||
# * Generate Cygwin (and/or MSYS2) packages for distribution.
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Configuration.
|
||||
|
||||
## Component Versions
|
||||
#
|
||||
# These options are self explanatory, but *must* correspond to a
|
||||
# supported version within the "musl-cross-make" repository. One
|
||||
# other factor to consider is that kernel headers and musl libc
|
||||
# will be harvested from a "donor" toolchain; these versions do
|
||||
# not necessarily correspond to what is built here (yet, TODO).
|
||||
#
|
||||
GCC_VER=9.3.0
|
||||
BINUTILS_VER=2.34
|
||||
MUSL_VER=git-0a005f499cf39822166dd4db3d2d31f0639f1b1b
|
||||
GMP_VER=6.2.0
|
||||
MPC_VER=1.1.0
|
||||
MPFR_VER=4.1.0
|
||||
LINUX_VER=5.4.50 # TODO: proper install, no rsync
|
||||
|
||||
## Directories
|
||||
#
|
||||
# By default, all toolchains that can be built, are built. This
|
||||
# requires a significant amount of disk space. Please ensure you
|
||||
# have at least 50GB of free disk space in these directories:
|
||||
#
|
||||
base="/tmp/winner_src" # base source directory
|
||||
huge="/tmp/winner_bld" # base build directory
|
||||
logs="/tmp/winner_log" # suite build log directory
|
||||
zips="/tmp/winner_bin" # completed toolchains go here
|
||||
|
||||
## Toolchain Mirror
|
||||
#
|
||||
# If you have access to an x86_64 Linux machine, or one that has
|
||||
# an x86_64 QEMU user-mode emulator registered in 'binfmt_misc',
|
||||
# you will always be using the latest available software.
|
||||
#
|
||||
musl=https://more.musl.cc # more.musl.cc or mirror
|
||||
|
||||
## Toolchain Naming Conventions
|
||||
#
|
||||
# The musl.cc toolchains follow a simple naming convention: all
|
||||
# cross compilers are suffixed with '-cross', native '-native'.
|
||||
# If you're using a different mirror or convention, set it here.
|
||||
#
|
||||
csuf=-cross # cross suffix
|
||||
nsuf=-native # native suffix
|
||||
|
||||
## Toolchain Tuples
|
||||
#
|
||||
# Values can be found at 'https://more.musl.cc/' where the $user
|
||||
# variable corresponds to your build platform, and $host to your
|
||||
# intended Windows development environment. Note that unless the
|
||||
# website says otherwise, only the 'i686-linux-musl' toolchain
|
||||
# directory is up-to-date. If you can't find what you're looking
|
||||
# for you must build a MinGW-w64 suitable toolchain from source.
|
||||
#
|
||||
user=i686-linux-musl # platform that builds suite
|
||||
host=i686-w64-mingw32 # platform that runs suite
|
||||
|
||||
## Build Environment
|
||||
#
|
||||
# This variable is extended during the toolchain download step.
|
||||
#
|
||||
kale="${base}/${host}${csuf}/bin:${base}/${user}${csuf}/bin";
|
||||
|
||||
## Repositories
|
||||
#
|
||||
# The build infrastructure used is called "musl-cross-make" and
|
||||
# is upstream https://github.com/richfelker/musl-cross-make, but
|
||||
# this version is incompatible with the current script. It's out
|
||||
# of date, too, so please leave the default unless you fork it.
|
||||
#
|
||||
name=musl-cross-make
|
||||
repo=https://git.zv.io/toolchains/${name}
|
||||
brch=master # branch name (no assumptions!)
|
||||
|
||||
## Suite Targets
|
||||
#
|
||||
# Now that RISC-V patches are (unofficially) merged into musl, a
|
||||
# single text file with target tuples (which comprise the suite)
|
||||
# may now be used. Modify this with e.g. a pastebin link if you
|
||||
# wish to use a different list (this one is self-updating).
|
||||
#
|
||||
list=${repo}/raw/${brch}/scripts/triples.txt
|
||||
filt=tuples.txt # filename of saved tuples list
|
||||
|
||||
## Suite Configuration
|
||||
#
|
||||
# To facilitate users' needs in customizing the toolchain suite,
|
||||
# a configuration file is embedded below. These settings *must*
|
||||
# be supported by the repository specified above.
|
||||
#
|
||||
# Note: items that are prefixed/suffixed with double underscores
|
||||
# are automatically populated later. Do not modify them here!
|
||||
#
|
||||
conf=$(cat <<'EOF'
|
||||
STAT = -static --static
|
||||
FLAG = -g0 -O2 -fno-align-functions -fno-align-jumps -fno-align-loops -fno-align-labels
|
||||
|
||||
ifneq ($(NATIVE),)
|
||||
COMMON_CONFIG += CC="$(HOST)-gcc ${STAT}" CXX="$(HOST)-g++ ${STAT}" FC="$(HOST)-gfortran ${STAT}"
|
||||
else
|
||||
COMMON_CONFIG += CC="gcc ${STAT}" CXX="g++ ${STAT}" FC="gfortran ${STAT}"
|
||||
endif
|
||||
COMMON_CONFIG += CFLAGS="${FLAG}" CXXFLAGS="${FLAG}" FFLAGS="${FLAG}" LDFLAGS="-s ${STAT}"
|
||||
COMMON_CONFIG += --disable-nls --disable-bootstrap --build=__USER__ --host=__HOST__ --target=__TARG__
|
||||
|
||||
GCC_VER = __GCC_VER__
|
||||
BINUTILS_VER = __BINUTILS_VER__
|
||||
MUSL_VER = __MUSL_VER__
|
||||
GMP_VER = __GMP_VER__
|
||||
MPC_VER = __MPC_VER__
|
||||
MPFR_VER = __MPFR_VER__
|
||||
LINUX_VER = __LINUX_VER__
|
||||
EOF
|
||||
);
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Subroutines.
|
||||
|
||||
# Download preliminary toolchains.
|
||||
#
|
||||
get_tool ()
|
||||
{
|
||||
mkdir -p "${base}";
|
||||
|
||||
# host
|
||||
if [ ! -d "${base}/${host}${csuf}" ]; then
|
||||
curl ${musl}/${user}/${host}${csuf}.tgz \
|
||||
| tar 2>/dev/null -C "${base}" -xzf -;
|
||||
(
|
||||
cd "${base}/${host}${csuf}/bin";
|
||||
find . -maxdepth 1 -type f | while read k; do
|
||||
ln -sf ${k} ${k#*-*-*-};
|
||||
done;
|
||||
)
|
||||
fi
|
||||
|
||||
# build
|
||||
if [ ! -d "${base}/${user}${csuf}" ]; then
|
||||
curl ${musl}/${user}/${user}${csuf}.tgz \
|
||||
| tar 2>/dev/null -C "${base}" -xzf -;
|
||||
fi
|
||||
}
|
||||
|
||||
# Clone a suitable "musl-cross-make" repository.
|
||||
#
|
||||
get_repo ()
|
||||
{
|
||||
[ -d "${base}" ] || exit 1;
|
||||
[ ! -d "${base}/${name}" ] || return;
|
||||
git clone ${repo} "${base}/${name}";
|
||||
}
|
||||
|
||||
# Overwrite any existing configuration (config.mak) template.
|
||||
#
|
||||
get_conf ()
|
||||
{
|
||||
[ -d "${base}/${name}" ] || exit 1;
|
||||
printf > "${base}/${name}/config.mak" "%s\n" \
|
||||
"${conf}";
|
||||
}
|
||||
|
||||
# Fetch an up-to-date list of possible target tuples. Allow the
|
||||
# user to edit this list, if the line is uncommented, before DL.
|
||||
#
|
||||
get_list ()
|
||||
{
|
||||
[ ! -f "${base}/${filt}" ] || return;
|
||||
curl -o "${base}/${filt}" ${list};
|
||||
sed -i "${base}/${filt}" -e '/mingw/d';
|
||||
#nano "${base}/${filt}";
|
||||
}
|
||||
|
||||
# Download all necessary target toolchains.
|
||||
#
|
||||
get_targ ()
|
||||
{
|
||||
# targets (if different from build)
|
||||
cat "${base}/${filt}" | grep -v "#" | while read k; do
|
||||
if [ ! -d "${base}/${k}${csuf}" ]; then
|
||||
curl ${musl}/${user}/${k}${csuf}.tgz \
|
||||
| tar 2>/dev/null -C "${base}" -xzf -;
|
||||
fi
|
||||
done;
|
||||
}
|
||||
|
||||
# Build the compiler suite without musl or kernel headers. Note:
|
||||
# the '-ik' in the 'make' command is required to avoid issues in
|
||||
# areas that have not yet been investigated but don't affect the
|
||||
# correctness of the resulting toolchain.
|
||||
#
|
||||
run_make ()
|
||||
{
|
||||
mkdir -p "${huge}";
|
||||
mkdir -p "${logs}";
|
||||
|
||||
cat "${base}/${filt}" | grep -v "#" | while read k; do
|
||||
|
||||
get_conf; sed -i "${base}/${name}/config.mak" \
|
||||
-e "s@__USER__@${user}@" \
|
||||
-e "s@__HOST__@${host}@" \
|
||||
-e "s@__TARG__@${k}@" \
|
||||
\
|
||||
-e "s@__GCC_VER__@${GCC_VER}@" \
|
||||
-e "s@__BINUTILS_VER__@${BINUTILS_VER}@" \
|
||||
-e "s@__MUSL_VER__@${MUSL_VER}@" \
|
||||
-e "s@__GMP_VER__@${GMP_VER}@" \
|
||||
-e "s@__MPC_VER__@${MPC_VER}@" \
|
||||
-e "s@__MPFR_VER__@${MPFR_VER}@" \
|
||||
-e "s@__LINUX_VER__@@";
|
||||
|
||||
if [ ! -d "${huge}/${k}${csuf}" ]; then
|
||||
PATH="${kale}:${base}/${k}${csuf}/bin:${PATH}" \
|
||||
\
|
||||
CC="${host}-gcc" \
|
||||
CXX="${host}-g++" \
|
||||
RANLIB="${host}-ranlib" \
|
||||
\
|
||||
CC_FOR_BUILD="${user}-gcc" \
|
||||
CXX_FOR_BUILD="${user}-g++" \
|
||||
RANLIB_FOR_BUILD="${user}-ranlib" \
|
||||
\
|
||||
CC_FOR_TARGET="${k}-gcc" \
|
||||
CXX_FOR_TARGET="${k}-g++" \
|
||||
RANLIB_FOR_TARGET="${k}-ranlib" \
|
||||
\
|
||||
make -ik -C "${base}/${name}" -O install \
|
||||
TARGET=${k} OUTPUT="${huge}/${k}${csuf}" \
|
||||
2>&1 | tee "${logs}/${k}${csuf}.log";
|
||||
fi
|
||||
|
||||
done;
|
||||
}
|
||||
|
||||
# Synchronize a donor toolchain's libraries and headers (for the
|
||||
# sole purposes of musl and kernel headers) with the newly-built
|
||||
# Windows-hosted toolchain.
|
||||
#
|
||||
run_sync ()
|
||||
{
|
||||
cat "${base}/${filt}" | grep -v "#" | while read k; do
|
||||
sync=$(cat <<EOF
|
||||
${k}${csuf}/${k}/include/
|
||||
${k}${csuf}/${k}/lib/
|
||||
EOF
|
||||
);
|
||||
for n in ${sync}; do rsync -raz --ignore-existing \
|
||||
"${base}/${n}" "${huge}/${n}";
|
||||
done;
|
||||
done;
|
||||
}
|
||||
|
||||
# Windows does not appreciate symbolic links. Delete them. Then
|
||||
# pack the toolchains into zip files. They're ready for distro.
|
||||
#
|
||||
run_pack ()
|
||||
{
|
||||
mkdir -p "${zips}";
|
||||
|
||||
cat "${base}/${filt}" | grep -v "#" | while read k; do
|
||||
if [ ! -e "${zips}/${k}${csuf}.zip" ]; then
|
||||
(
|
||||
cd "${huge}";
|
||||
find ${k}${csuf} -type l -delete;
|
||||
zip -rq "${zips}/${k}${csuf}.zip" ${k}${csuf};
|
||||
)
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Driver.
|
||||
|
||||
get_tool; # Download initial toolchains.
|
||||
get_repo; # Clone "musl-cross-make" repo.
|
||||
get_conf; # Write toolchain configuration.
|
||||
get_list; # Generate list of targets.
|
||||
get_targ; # Fetch "donor" toolchains.
|
||||
|
||||
run_make; # Build specified toolchains.
|
||||
run_sync; # Harvest/inject "donor" organs.
|
||||
run_pack; # Pack output for distribution.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user