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15 Commits
v0.9.11 ... master

Author SHA1 Message Date
userdocs
3635262e45 bump default versions for gmp, mpc, and mpfr to latest 2025-07-27 01:34:35 +00:00
userdocs
5208eeb2df add support for latest versions of gmp, isl, mpc, and mpfr 2025-07-27 01:33:44 +00:00
userdocs
5b3b4ea504 add support Linux kernel 6.15.7 
added support for tested to work 6.15.7 of the Linux kernel version.
 2025-07-27 01:31:12 +00:00
Rich Felker
f5a188a976 drop config.sub replacement 
this was only done to fix some missing tuple matches (probably only
sh2eb) on very old gcc and binutils versions. instead of dropping an
arbitrary version of config.sub into every autoconf'd tree, add
patches for the only affected gcc and binutils versions that are
supported.
 2025-07-27 01:27:23 +00:00
userdocs
b97b5e7a61 add support config.sub a2287c3041a3 
Add hash for tested to work config.sub HEAD with sha a2287c3041a3, at
the time of this pull request.
 2025-07-27 01:26:09 +00:00
Rich Felker
4be756d35c update all static pie patches to ensure -static reached the linker 
on some targets, the logic for the compiler option -static seems not
to be processed when -pie is present. rather than playing
whack-a-mole, just ensure LD_PIE_SPEC specs always pass -static to ld
if either -static or -static-pie is present on the compiler driver
command line.

this may produce redundant -static arguments but it doesn't matter.
 2025-07-21 02:25:06 +00:00
Rich Felker
2398261280 add patches to fix riscv & s390x ld not binding PIE symbols at link time 
these should probably be backported to older binutils too, but they
don't apply as-is since the code has been refactored. I don't consider
this a high priority; use of old binutils should probably be treated
as deprecated at some point.
 2025-07-21 02:24:15 +00:00
userdocs
baad915870 add support for gcc 15.1.0 
This adds the patches from the previously tested gcc version 14.3.0
and they have been tested to successfully apply to 15.1.0 with no
issues.

The corresponding hash has been added.
 2025-07-21 00:19:03 +00:00
userdocs
b337fe6d1d add support for gcc 14.3.0 
This adds the patches from the previously tested gcc version 14.2.0
and they have been tested to successfully apply to 14.3.0 with no
issues. The libquadmath patch for GCC issue 116007 is not copied over
because it has already been applied upstream.

The corresponding hash has been added.
 2025-07-21 00:17:59 +00:00
Rich Felker
a77218fdaa add support for linux 6.x kernel urls as kernel headers source 
still needs hashes added to be useful.
 2025-07-20 23:42:13 +00:00
Rich Felker
038afb6dbd litecross: add missing arch name remapping for or1k from gcc to kernel 
this was overlooked long ago and makes it so kernel headers can't be
built & installed for or1k.
 2025-07-20 23:08:17 +00:00
rofl0r
5fea505f63 gcc-11*: fix calloc poison error when built with gcc12 on musl 
patch was picked from gcc git by @michaelforney and adapted
for GCC 11, and while it applies cleanly to gcc 11.2.0 and 11.3.0,
further modification was needed for gcc 11.5.0.

refs:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106102
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=3b21c21f3f5726823e19728fdd1571a14aae0fb3
 2025-07-20 23:02:01 +00:00
Rich Felker
14175d4a21 add gcc 14 patch to fix libquadmath build on ppc64 
this is the upstream patch for fixing gcc bug 116007. gcc 13 does not
seem to have the bug, and it should already be fixed in gcc 15 when we
add it.
 2025-07-20 22:06:10 +00:00
Rich Felker
4a01792295 bump default binutils version to 2.44 
this is needed to fix riscv64 builds with newer gcc versions, and
probably fixes other bugs too.
 2025-07-20 02:58:42 +00:00
Rich Felker
83b033668e add hash and forward-ported patches for binutils 2.44 2025-07-20 02:55:04 +00:00
48 changed files with 2462 additions and 17 deletions
Show Stats Expand all files Collapse all files

12
Makefile
View File

@ -2,12 +2,12 @@
SOURCES = sources
CONFIG_SUB_REV = 3d5db9ebe860
BINUTILS_VER = 2.33.1
BINUTILS_VER = 2.44
GCC_VER = 9.4.0
MUSL_VER = 1.2.5
GMP_VER = 6.1.2
MPC_VER = 1.1.0
MPFR_VER = 4.0.2
GMP_VER = 6.3.0
MPC_VER = 1.3.1
MPFR_VER = 4.2.2
LINUX_VER = headers-4.19.88-2
GNU_SITE = https://ftpmirror.gnu.org/gnu
@ -65,6 +65,7 @@ $(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/isl*)): SITE = $(ISL_SIT
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/binutils*)): SITE = $(BINUTILS_SITE)
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/gcc*)): SITE = $(GCC_SITE)/$(basename $(basename $(notdir $@)))
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/musl*)): SITE = $(MUSL_SITE)
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-6*)): SITE = $(LINUX_SITE)/v6.x
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-5*)): SITE = $(LINUX_SITE)/v5.x
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-4*)): SITE = $(LINUX_SITE)/v4.x
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-3*)): SITE = $(LINUX_SITE)/v3.x
@ -131,13 +132,12 @@ musl-git-%:
mv $@.tmp/$(patsubst %.orig,%,$@) $@
rm -rf $@.tmp
%: %.orig | $(SOURCES)/config.sub
%: %.orig
case "$@" in */*) exit 1 ;; esac
rm -rf $@.tmp
mkdir $@.tmp
( cd $@.tmp && $(COWPATCH) -I ../$< )
test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp && $(COWPATCH) -p1 )
if test -f $</configfsf.sub ; then cs=configfsf.sub ; elif test -f $</config.sub ; then cs=config.sub ; else exit 0 ; fi ; rm -f $@.tmp/$$cs && cp -f $(SOURCES)/config.sub $@.tmp/$$cs && chmod +x $@.tmp/$$cs
rm -rf $@
mv $@.tmp $@

1
hashes/binutils-2.44.tar.gz.sha1 Normal file
View File

@ -0,0 +1 @@
568ba0a286cf79520572c1597a203c1aafd462de binutils-2.44.tar.gz

1
hashes/config.sub.a2287c3041a3.sha1 Normal file
View File

@ -0,0 +1 @@
3adf4069b9eb2c9d90b98ba533b006dc49a008cf config.sub

1
hashes/gcc-14.3.0.tar.xz.sha1 Normal file
View File

@ -0,0 +1 @@
e33b9ffb8baf1528d72a8a26a1ee678928ca9121 gcc-14.3.0.tar.xz

1
hashes/gcc-15.1.0.tar.xz.sha1 Normal file
View File

@ -0,0 +1 @@
42017f9c1b53a345ea1214c32012609b29dba5a2 gcc-15.1.0.tar.xz

1
hashes/gmp-6.3.0.tar.xz.sha1 Normal file
View File

@ -0,0 +1 @@
b4043dd2964ab1a858109da85c44de224384f352 gmp-6.3.0.tar.xz

1
hashes/isl-0.27.tar.xz.sha1 Normal file
View File

@ -0,0 +1 @@
8778bdabc1fbebe392564440c1ebbaaa45cdaf85 isl-0.27.tar.xz

1
hashes/linux-6.15.7.tar.xz.sha1 Normal file
View File

@ -0,0 +1 @@
d97af2fed36305f0e7b24167baae9c8fcc7a01ec linux-6.15.7.tar.xz

1
hashes/mpc-1.3.1.tar.gz.sha1 Normal file
View File

@ -0,0 +1 @@
bac1c1fa79f5602df1e29e4684e103ad55714e02 mpc-1.3.1.tar.gz

1
hashes/mpfr-4.2.2.tar.xz.sha1 Normal file
View File

@ -0,0 +1 @@
a63a264b273a652e27518443640e69567da498ce mpfr-4.2.2.tar.xz

2
litecross/Makefile
View File

@ -258,7 +258,7 @@ install-gcc: | obj_gcc/.lc_built
ifneq ($(LINUX_SRCDIR),)
TARGET_ARCH = $(firstword $(subst -, ,$(TARGET)))
TARGET_ARCH_MANGLED = $(patsubst i%86,x86,$(patsubst aarch64%,arm64%,$(TARGET_ARCH)))
TARGET_ARCH_MANGLED = $(patsubst or1k,openrisc,$(patsubst i%86,x86,$(patsubst aarch64%,arm64%,$(TARGET_ARCH))))
LINUX_ARCH_LIST = $(sort $(notdir $(wildcard $(LINUX_SRCDIR)/arch/*)))
LINUX_ARCH = $(lastword $(foreach a,$(LINUX_ARCH_LIST),$(if $(filter $(a)%,$(TARGET_ARCH_MANGLED)),$(a))))
ifneq ($(LINUX_ARCH),)

196
patches/binutils-2.25.1/0012-configsub-sheb.diff Normal file
View File

@ -0,0 +1,196 @@
--- binutils-2.25.1.orig/config.sub
+++ binutils-2.25.1/config.sub
@@ -1,8 +1,8 @@
#! /bin/sh
# Configuration validation subroutine script.
-# Copyright 1992-2014 Free Software Foundation, Inc.
+# Copyright 1992-2016 Free Software Foundation, Inc.
-timestamp='2014-07-28'
+timestamp='2016-03-30'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -25,7 +25,7 @@
# of the GNU General Public License, version 3 ("GPLv3").
-# Please send patches with a ChangeLog entry to config-patches@gnu.org.
+# Please send patches to <config-patches@gnu.org>.
#
# Configuration subroutine to validate and canonicalize a configuration type.
# Supply the specified configuration type as an argument.
@@ -33,7 +33,7 @@
# Otherwise, we print the canonical config type on stdout and succeed.
# You can get the latest version of this script from:
-# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub
# This file is supposed to be the same for all GNU packages
# and recognize all the CPU types, system types and aliases
@@ -53,8 +53,7 @@
me=`echo "$0" | sed -e 's,.*/,,'`
usage="\
-Usage: $0 [OPTION] CPU-MFR-OPSYS
- $0 [OPTION] ALIAS
+Usage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS
Canonicalize a configuration name.
@@ -68,7 +67,7 @@
version="\
GNU config.sub ($timestamp)
-Copyright 1992-2014 Free Software Foundation, Inc.
+Copyright 1992-2016 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -117,7 +116,7 @@
case $maybe_os in
nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
- knetbsd*-gnu* | netbsd*-gnu* | \
+ knetbsd*-gnu* | netbsd*-gnu* | netbsd*-eabi* | \
kopensolaris*-gnu* | \
storm-chaos* | os2-emx* | rtmk-nova*)
os=-$maybe_os
@@ -255,12 +254,13 @@
| arc | arceb \
| arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
| avr | avr32 \
+ | ba \
| be32 | be64 \
| bfin \
| c4x | c8051 | clipper \
| d10v | d30v | dlx | dsp16xx \
- | epiphany \
- | fido | fr30 | frv \
+ | e2k | epiphany \
+ | fido | fr30 | frv | ft32 \
| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
| hexagon \
| i370 | i860 | i960 | ia64 \
@@ -302,9 +302,10 @@
| pdp10 | pdp11 | pj | pjl \
| powerpc | powerpc64 | powerpc64le | powerpcle \
| pyramid \
+ | riscv32 | riscv64 \
| rl78 | rx \
| score \
- | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
+ | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[234]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
| sh64 | sh64le \
| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
@@ -312,6 +313,7 @@
| tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \
| ubicom32 \
| v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \
+ | visium \
| we32k \
| x86 | xc16x | xstormy16 | xtensa \
| z8k | z80)
@@ -326,6 +328,9 @@
c6x)
basic_machine=tic6x-unknown
;;
+ leon|leon[3-9])
+ basic_machine=sparc-$basic_machine
+ ;;
m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip)
basic_machine=$basic_machine-unknown
os=-none
@@ -371,12 +376,13 @@
| alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
| arm-* | armbe-* | armle-* | armeb-* | armv*-* \
| avr-* | avr32-* \
+ | ba-* \
| be32-* | be64-* \
| bfin-* | bs2000-* \
| c[123]* | c30-* | [cjt]90-* | c4x-* \
| c8051-* | clipper-* | craynv-* | cydra-* \
| d10v-* | d30v-* | dlx-* \
- | elxsi-* \
+ | e2k-* | elxsi-* \
| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
| h8300-* | h8500-* \
| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
@@ -423,12 +429,13 @@
| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
| pyramid-* \
+ | riscv32-* | riscv64-* \
| rl78-* | romp-* | rs6000-* | rx-* \
| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
| sparclite-* \
- | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \
+ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx*-* \
| tahoe-* \
| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
| tile*-* \
@@ -436,6 +443,7 @@
| ubicom32-* \
| v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \
| vax-* \
+ | visium-* \
| we32k-* \
| x86-* | x86_64-* | xc16x-* | xps100-* \
| xstormy16-* | xtensa*-* \
@@ -512,6 +520,9 @@
basic_machine=i386-pc
os=-aros
;;
+ asmjs)
+ basic_machine=asmjs-unknown
+ ;;
aux)
basic_machine=m68k-apple
os=-aux
@@ -773,6 +784,9 @@
basic_machine=m68k-isi
os=-sysv
;;
+ leon-*|leon[3-9]-*)
+ basic_machine=sparc-`echo $basic_machine | sed 's/-.*//'`
+ ;;
m68knommu)
basic_machine=m68k-unknown
os=-linux
@@ -1364,11 +1378,11 @@
| -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \
| -sym* | -kopensolaris* | -plan9* \
| -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
- | -aos* | -aros* \
+ | -aos* | -aros* | -cloudabi* | -sortix* \
| -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
| -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
| -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
- | -bitrig* | -openbsd* | -solidbsd* \
+ | -bitrig* | -openbsd* | -solidbsd* | -libertybsd* \
| -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
| -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
| -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
@@ -1384,7 +1398,8 @@
| -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
| -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
| -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
- | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*)
+ | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* \
+ | -onefs* | -tirtos*)
# Remember, each alternative MUST END IN *, to match a version number.
;;
-qnx*)
@@ -1515,6 +1530,8 @@
os=-dicos
;;
-nacl*)
+ ;;
+ -ios)
;;
-none)
;;

586
patches/binutils-2.44/0001-j2.diff Normal file
View File

@ -0,0 +1,586 @@
diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c
--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400
@@ -298,6 +298,8 @@
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
.#define bfd_mach_sh2a_or_sh4 0x2a3
.#define bfd_mach_sh2a_or_sh3e 0x2a4
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+.#define bfd_mach_shj2 0x2c
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
.#define bfd_mach_sh3_nommu 0x31
Only in binutils-2.32/bfd: archures.c.orig
Only in binutils-2.32/bfd: archures.c.rej
diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h
--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400
@@ -2197,6 +2197,8 @@
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
#define bfd_mach_sh2a_or_sh4 0x2a3
#define bfd_mach_sh2a_or_sh3e 0x2a4
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+#define bfd_mach_shj2 0x2c
#define bfd_mach_sh2e 0x2e
#define bfd_mach_sh3 0x30
#define bfd_mach_sh3_nommu 0x31
Only in binutils-2.32/bfd: bfd-in2.h.orig
Only in binutils-2.32/bfd: bfd-in2.h.rej
diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c
--- binutils-2.44.orig/bfd/cpu-sh.c
+++ binutils-2.44/bfd/cpu-sh.c
@@ -63,7 +63,9 @@
N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", false, arch_info_struct + 16),
N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", false, arch_info_struct + 17),
N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", false, arch_info_struct + 18),
- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, NULL)
+ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, arch_info_struct + 19),
+ N (bfd_mach_shj2, "j2", false, arch_info_struct + 20),
+ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-or-sh3e-or-j2", false, NULL),
};
const bfd_arch_info_type bfd_sh_arch =
@@ -99,6 +101,8 @@
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
{ 0, 0, 0 } /* Terminator. */
};
Only in binutils-2.32/bfd: cpu-sh.c.orig
Only in binutils-2.32/bfd: cpu-sh.c.rej
diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c
--- binutils-2.44.orig/binutils/readelf.c
+++ binutils-2.44/binutils/readelf.c
@@ -4687,6 +4687,12 @@
case EF_SH2A_SH3E:
out = stpcpy (out, ", sh2a-or-sh3e");
break;
+ case EF_SHJ2:
+ out = stpcpy (out, ", j2");
+ break;
+ case EF_SH2A_SH3_SHJ2:
+ out = stpcpy (out, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu");
+ break;
default:
out = stpcpy (out, _(", unknown ISA"));
break;
Only in binutils-2.32/binutils: readelf.c.orig
diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c
--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400
@@ -1251,6 +1251,8 @@
ptr++;
}
get_operand (&ptr, operand + 2);
+ if (strcmp (info->name,"cas") == 0)
+ operand[2].type = A_IND_0;
}
else
{
@@ -1790,7 +1792,10 @@
goto fail;
reg_m = 4;
break;
-
+ case A_IND_0:
+ if (user->reg != 0)
+ goto fail;
+ break;
default:
printf (_("unhandled %d\n"), arg);
goto fail;
Only in binutils-2.32/gas/config: tc-sh.c.orig
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400
@@ -12,8 +12,6 @@
sh2a_nofpu_or_sh3_nommu:
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400
@@ -12,7 +12,7 @@
sh2a_nofpu_or_sh4_nommu_nofpu:
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -119,8 +119,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400
@@ -64,7 +64,7 @@
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -171,8 +171,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh2a-or-sh3e
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -124,8 +124,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400
@@ -39,7 +39,7 @@
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -150,8 +150,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400
@@ -16,7 +16,7 @@
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -140,8 +140,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400
@@ -12,7 +12,7 @@
sh3_dsp:
! Instructions introduced into sh3-dsp
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -152,8 +152,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400
@@ -26,7 +26,7 @@
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -133,8 +133,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh3
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -128,8 +128,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400
@@ -12,7 +12,7 @@
sh3e:
! Instructions introduced into sh3e
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -132,8 +132,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400
@@ -12,7 +12,7 @@
sh4_nofpu:
! Instructions introduced into sh4-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -136,8 +136,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400
@@ -24,7 +24,7 @@
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -139,8 +139,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400
@@ -17,7 +17,7 @@
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -145,8 +145,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400
@@ -19,7 +19,7 @@
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -143,8 +143,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh4a
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -147,8 +147,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400
@@ -48,7 +48,7 @@
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -202,8 +202,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h
--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400
@@ -39,6 +39,7 @@
#define EF_SH2E 11
#define EF_SH4A 12
#define EF_SH2A 13
+#define EF_SHJ2 14
#define EF_SH4_NOFPU 16
#define EF_SH4A_NOFPU 17
@@ -50,6 +51,7 @@
#define EF_SH2A_SH3_NOFPU 22
#define EF_SH2A_SH4 23
#define EF_SH2A_SH3E 24
+#define EF_SH2A_SH3_SHJ2 25
/* This one can only mix in objects from other EF_SH5 objects. */
#define EF_SH5 10
@@ -72,7 +74,8 @@
/* EF_SH2E */ bfd_mach_sh2e , \
/* EF_SH4A */ bfd_mach_sh4a , \
/* EF_SH2A */ bfd_mach_sh2a , \
-/* 14, 15 */ 0, 0, \
+/* EF_SHJ2 */ bfd_mach_shj2 , \
+/* 15 */ 0, \
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
@@ -81,7 +84,8 @@
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
/* Convert arch_sh* into EF_SH*. */
int sh_find_elf_flags (unsigned int arch_set);
diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c
--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500
+++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400
@@ -856,6 +856,9 @@
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
+ case A_IND_0:
+ fprintf_fn (stream, "@r0");
+ break;
default:
abort ();
}
Only in binutils-2.32/opcodes: sh-dis.c.orig
diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h
--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500
+++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400
@@ -191,7 +191,8 @@
FPUL_N,
FPUL_M,
FPSCR_N,
- FPSCR_M
+ FPSCR_M,
+ A_IND_0
}
sh_arg_type;
@@ -215,9 +216,11 @@
#define arch_sh4_base (1 << 5)
#define arch_sh4a_base (1 << 6)
#define arch_sh2a_base (1 << 7)
-#define arch_sh_base_mask MASK (0, 7)
+#define arch_shj2_base (1 << 8)
+#define arch_sh2a_sh3_shj2_base (1 << 9)
+#define arch_sh_base_mask MASK (0, 9)
-/* Bits 8 ... 24 are currently free. */
+/* Bits 10 ... 24 are currently free. */
/* This is an annotation on instruction types, but we
abuse the arch field in instructions to denote it. */
@@ -255,6 +258,8 @@
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
@@ -319,7 +324,8 @@
#define arch_sh2_up (arch_sh2 \
| arch_sh2e_up \
| arch_sh2a_nofpu_or_sh3_nommu_up \
- | arch_sh_dsp_up)
+ | arch_sh_dsp_up \
+ | arch_shj2_up)
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
| arch_sh2a_or_sh3e_up \
@@ -345,6 +351,12 @@
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
| arch_sh4a_up \
| arch_sh4al_dsp_up)
+#define arch_shj2_up ( arch_shj2)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
+ | arch_sh2a_or_sh3e_up \
+ | arch_sh3_nommu_up \
+ | arch_shj2_up)
/* Right branches. */
#define arch_sh2e_up (arch_sh2e \
@@ -713,9 +725,9 @@
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
@@ -1193,7 +1205,7 @@
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
-
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
{ 0, {0}, {0}, 0 }
};
Only in binutils-2.32/opcodes: sh-opc.h.orig

33
patches/binutils-2.44/0002-sh-fdpic-pr31619.diff Normal file
View File

@ -0,0 +1,33 @@
--- binutils-2.33.1/bfd/elf32-sh.c.orig 2024-04-04 23:11:28.739136261 +0900
+++ binutils-2.33.1/bfd/elf32-sh.c 2024-04-08 23:14:24.496915074 +0900
@@ -61,7 +61,7 @@
not. If the symbol is protected, we want the local address, but
its function descriptor must be assigned by the dynamic linker. */
#define SYMBOL_FUNCDESC_LOCAL(INFO, H) \
- (SYMBOL_REFERENCES_LOCAL (INFO, H) \
+ (!(H) || (H)->dynindx < 0 || (H)->forced_local \
|| ! elf_hash_table (INFO)->dynamic_sections_created)
#define SH_PARTIAL32 TRUE
@@ -4405,20 +4405,6 @@
/* Undefined weak symbol which will not be dynamically
resolved later; leave it at zero. */
goto funcdesc_leave_zero;
- else if (SYMBOL_CALLS_LOCAL (info, h)
- && ! SYMBOL_FUNCDESC_LOCAL (info, h))
- {
- /* If the symbol needs a non-local function descriptor
- but binds locally (i.e., its visibility is
- protected), emit a dynamic relocation decayed to
- section+offset. This is an optimization; the dynamic
- linker would resolve our function descriptor request
- to our copy of the function anyway. */
- dynindx = elf_section_data (h->root.u.def.section
- ->output_section)->dynindx;
- relocation += h->root.u.def.section->output_offset
- + h->root.u.def.value;
- }
else if (! SYMBOL_FUNCDESC_LOCAL (info, h))
{
/* If the symbol is dynamic and there will be dynamic

45
patches/binutils-2.44/0003-riscv-pie-symbol-binding.diff Normal file
View File

@ -0,0 +1,45 @@
Patch-Source: https://sourceware.org/git/?p=binutils-gdb.git;a=patch;h=39c7793ba8bef5aab358511b22764081959cb2ff
From 39c7793ba8bef5aab358511b22764081959cb2ff Mon Sep 17 00:00:00 2001
From: Linsen Zhou <i@lin.moe>
Date: Tue, 8 Jul 2025 06:34:18 +0800
Subject: [PATCH] RISC-V: Bind defined symbol locally in PIE
Reference commit 1dcb9720d62cd053a72c31881b7724ce9f74332c
bfd/
* elfnn-riscv.c (RISCV_COPY_INPUT_RELOC): Bind defined symbol
locally in PIE.
ld/
* testsuite/ld-riscv-elf/pie-bind-locally-a.s: New test source.
* testsuite/ld-riscv-elf/pie-bind-locally-b.s: Likewise.
* testsuite/ld-riscv-elf/pie-bind-locally-rv32.d: New testcase.
* testsuite/ld-riscv-elf/pie-bind-locally-rv64.d: Likewise.
Signed-off-by: Linsen Zhou <i@lin.moe>
---
bfd/elfnn-riscv.c | 2 +-
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 3 +++
ld/testsuite/ld-riscv-elf/pie-bind-locally-a.s | 5 +++++
ld/testsuite/ld-riscv-elf/pie-bind-locally-b.s | 8 ++++++++
ld/testsuite/ld-riscv-elf/pie-bind-locally-rv32.d | 10 ++++++++++
ld/testsuite/ld-riscv-elf/pie-bind-locally-rv64.d | 10 ++++++++++
6 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 ld/testsuite/ld-riscv-elf/pie-bind-locally-a.s
create mode 100644 ld/testsuite/ld-riscv-elf/pie-bind-locally-b.s
create mode 100644 ld/testsuite/ld-riscv-elf/pie-bind-locally-rv32.d
create mode 100644 ld/testsuite/ld-riscv-elf/pie-bind-locally-rv64.d
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 790f0397cf5..2fd01299249 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -99,7 +99,7 @@
((H) != NULL \
&& (H)->dynindx != -1 \
&& (!bfd_link_pic (INFO) \
- || !SYMBOLIC_BIND ((INFO), (H)) \
+ || !(bfd_link_pie ((INFO)) || SYMBOLIC_BIND ((INFO), (H))) \
|| !(H)->def_regular))
/* True if this is actually a static link, or it is a -Bsymbolic link

13
patches/binutils-2.44/0004-s390x-pie-symbol-binding.diff Normal file
View File

@ -0,0 +1,13 @@
See riscv-pie.patch
--- a/bfd/elf64-s390.c
+++ b/bfd/elf64-s390.c
@@ -2953,7 +2953,7 @@ elf_s390_relocate_section (bfd *output_bfd,
|| r_type == R_390_PC32DBL
|| r_type == R_390_PC64
|| !bfd_link_pic (info)
- || !SYMBOLIC_BIND (info, h)
+ || !(bfd_link_pie (info) || SYMBOLIC_BIND (info, h))
|| !h->def_regular))
{
outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);

2
patches/gcc-10.3.0/0004-static-pie.diff
View File

@ -80,7 +80,7 @@ index e6887590ae2..df6e3965f13 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

2
patches/gcc-11.2.0/0004-static-pie.diff
View File

@ -80,7 +80,7 @@ index 3c81c5798d8..cd96eac5d12 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

110
patches/gcc-11.2.0/0010-poisoned-calloc.diff Normal file
View File

@ -0,0 +1,110 @@
From de6f402a54f7e6a3f8a79d723a25724e6274cc3e Mon Sep 17 00:00:00 2001
From: Sergei Trofimovich <siarheit@google.com>
Date: Mon, 27 Jun 2022 13:27:24 +0100
Subject: [PATCH] c++: avoid <memory> poisoning on musl [PR106102]
On musl <pthread.h> uses calloc() (via <sched.h>). <memory> includes
it indirectly and exposes use of poisoned calloc() when module code
is built:
/build/build/./prev-gcc/xg++ ... ../../gcc-13-20220626/gcc/cp/mapper-resolver.cc
In file included from /<<NIX>>/musl-1.2.3-dev/include/pthread.h:30,
from /build/build/prev-x86_64-unknown-linux-musl/libstdc++-v3/include/x86_64-unknown-linux-musl/bits/gthr-default.h:35,
....
from /build/build/prev-x86_64-unknown-linux-musl/libstdc++-v3/include/memory:77,
from ../../gcc-13-20220626/gcc/../libcody/cody.hh:24,
from ../../gcc-13-20220626/gcc/cp/../../c++tools/resolver.h:25,
from ../../gcc-13-20220626/gcc/cp/../../c++tools/resolver.cc:23,
from ../../gcc-13-20220626/gcc/cp/mapper-resolver.cc:32:
/<<NIX>>/musl-1.2.3-dev/include/sched.h:84:7: error: attempt to use poisoned "calloc"
84 | void *calloc(size_t, size_t);
| ^
/<<NIX>>/musl-1.2.3-dev/include/sched.h:124:36: error: attempt to use poisoned "calloc"
124 | #define CPU_ALLOC(n) ((cpu_set_t *)calloc(1,CPU_ALLOC_SIZE(n)))
| ^
gcc/cp/
PR c++/106102
* mapper-client.cc: Include <memory> via "system.h".
* mapper-resolver.cc: Ditto.
* module.cc: Ditto.
libcc1/
PR c++/106102
* libcc1plugin.cc: Include <memory> via "system.h".
* libcp1plugin.cc: Ditto.
(cherry picked from commit 3b21c21f3f5726823e19728fdd1571a14aae0fb3)
---
gcc/cp/mapper-client.cc | 1 +
gcc/cp/mapper-resolver.cc | 1 +
gcc/cp/module.cc | 1 +
libcc1/libcc1plugin.cc | 1 +
libcc1/libcp1plugin.cc | 1 +
5 files changed, 5 insertions(+)
diff --git a/gcc/cp/mapper-client.cc b/gcc/cp/mapper-client.cc
index 8603a886a09..fe9544b5ba4 100644
--- a/gcc/cp/mapper-client.cc
+++ b/gcc/cp/mapper-client.cc
@@ -27,6 +27,7 @@ along with GCC; see the file COPYING3. If not see
#define INCLUDE_STRING
#define INCLUDE_VECTOR
#define INCLUDE_MAP
+#define INCLUDE_UNIQUE_PTR
#include "system.h"
#include "line-map.h"
diff --git a/gcc/cp/mapper-resolver.cc b/gcc/cp/mapper-resolver.cc
index e3d29fb5ada..e70d1b4ae2c 100644
--- a/gcc/cp/mapper-resolver.cc
+++ b/gcc/cp/mapper-resolver.cc
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3. If not see
#define INCLUDE_VECTOR
#define INCLUDE_ALGORITHM
#define INCLUDE_MAP
+#define INCLUDE_UNIQUE_PTR
#include "system.h"
// We don't want or need to be aware of networking
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index cebf9c35c1d..5c5d02bb523 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -202,6 +202,7 @@ Classes used:
#define _DEFAULT_SOURCE 1 /* To get TZ field of struct tm, if available. */
#include "config.h"
+#define INCLUDE_UNIQUE_PTR
#define INCLUDE_STRING
#define INCLUDE_VECTOR
#include "system.h"
diff --git a/libcc1/libcc1plugin.cc b/libcc1/libcc1plugin.cc
index 12ab5a57c8d..bdd0bdabe77 100644
--- a/libcc1/libcc1plugin.cc
+++ b/libcc1/libcc1plugin.cc
@@ -31,6 +31,7 @@
#undef PACKAGE_TARNAME
#undef PACKAGE_VERSION
+#define INCLUDE_UNIQUE_PTR
#include "gcc-plugin.h"
#include "system.h"
#include "coretypes.h"
diff --git a/libcc1/libcp1plugin.cc b/libcc1/libcp1plugin.cc
index 83dab7f58b1..e2d5039a0a1 100644
--- a/libcc1/libcp1plugin.cc
+++ b/libcc1/libcp1plugin.cc
@@ -32,6 +32,7 @@
#undef PACKAGE_TARNAME
#undef PACKAGE_VERSION
+#define INCLUDE_UNIQUE_PTR
#include "gcc-plugin.h"
#include "system.h"
#include "coretypes.h"
--
2.42.0

2
patches/gcc-11.5.0/0004-static-pie.diff
View File

@ -80,7 +80,7 @@ index 3c81c5798d8..cd96eac5d12 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

111
patches/gcc-11.5.0/0010-poisoned-calloc.diff Normal file
View File

@ -0,0 +1,111 @@
From de6f402a54f7e6a3f8a79d723a25724e6274cc3e Mon Sep 17 00:00:00 2001
From: Sergei Trofimovich <siarheit@google.com>
Date: Mon, 27 Jun 2022 13:27:24 +0100
Subject: [PATCH] c++: avoid <memory> poisoning on musl [PR106102]
On musl <pthread.h> uses calloc() (via <sched.h>). <memory> includes
it indirectly and exposes use of poisoned calloc() when module code
is built:
/build/build/./prev-gcc/xg++ ... ../../gcc-13-20220626/gcc/cp/mapper-resolver.cc
In file included from /<<NIX>>/musl-1.2.3-dev/include/pthread.h:30,
from /build/build/prev-x86_64-unknown-linux-musl/libstdc++-v3/include/x86_64-unknown-linux-musl/bits/gthr-default.h:35,
....
from /build/build/prev-x86_64-unknown-linux-musl/libstdc++-v3/include/memory:77,
from ../../gcc-13-20220626/gcc/../libcody/cody.hh:24,
from ../../gcc-13-20220626/gcc/cp/../../c++tools/resolver.h:25,
from ../../gcc-13-20220626/gcc/cp/../../c++tools/resolver.cc:23,
from ../../gcc-13-20220626/gcc/cp/mapper-resolver.cc:32:
/<<NIX>>/musl-1.2.3-dev/include/sched.h:84:7: error: attempt to use poisoned "calloc"
84 | void *calloc(size_t, size_t);
| ^
/<<NIX>>/musl-1.2.3-dev/include/sched.h:124:36: error: attempt to use poisoned "calloc"
124 | #define CPU_ALLOC(n) ((cpu_set_t *)calloc(1,CPU_ALLOC_SIZE(n)))
| ^
gcc/cp/
PR c++/106102
* mapper-client.cc: Include <memory> via "system.h".
* mapper-resolver.cc: Ditto.
* module.cc: Ditto.
libcc1/
PR c++/106102
* libcc1plugin.cc: Include <memory> via "system.h".
* libcp1plugin.cc: Ditto.
(cherry picked from commit 3b21c21f3f5726823e19728fdd1571a14aae0fb3)
---
gcc/cp/mapper-client.cc | 1 +
gcc/cp/mapper-resolver.cc | 1 +
gcc/cp/module.cc | 1 +
libcc1/libcc1plugin.cc | 1 +
libcc1/libcp1plugin.cc | 1 +
5 files changed, 5 insertions(+)
diff --git a/gcc/cp/mapper-client.cc b/gcc/cp/mapper-client.cc
index 8603a886a09..fe9544b5ba4 100644
--- a/gcc/cp/mapper-client.cc
+++ b/gcc/cp/mapper-client.cc
@@ -27,6 +27,7 @@ along with GCC; see the file COPYING3. If not see
#define INCLUDE_STRING
#define INCLUDE_VECTOR
#define INCLUDE_MAP
+#define INCLUDE_UNIQUE_PTR
#include "system.h"
#include "line-map.h"
diff --git a/gcc/cp/mapper-resolver.cc b/gcc/cp/mapper-resolver.cc
index e3d29fb5ada..e70d1b4ae2c 100644
--- a/gcc/cp/mapper-resolver.cc
+++ b/gcc/cp/mapper-resolver.cc
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3. If not see
#define INCLUDE_VECTOR
#define INCLUDE_ALGORITHM
#define INCLUDE_MAP
+#define INCLUDE_UNIQUE_PTR
#include "system.h"
// We don't want or need to be aware of networking
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index cebf9c35c1d..5c5d02bb523 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -202,6 +202,7 @@ Classes used:
#define _DEFAULT_SOURCE 1 /* To get TZ field of struct tm, if available. */
#include "config.h"
+#define INCLUDE_UNIQUE_PTR
#define INCLUDE_STRING
#define INCLUDE_VECTOR
#include "system.h"
diff --git a/libcc1/libcc1plugin.cc b/libcc1/libcc1plugin.cc
index 12ab5a57c8d..bdd0bdabe77 100644
--- a/libcc1/libcc1plugin.cc
+++ b/libcc1/libcc1plugin.cc
@@ -33,6 +33,8 @@
#define INCLUDE_MEMORY
#define INCLUDE_VECTOR
+#define INCLUDE_UNIQUE_PTR
+
#include "gcc-plugin.h"
#include "system.h"
#include "coretypes.h"
diff --git a/libcc1/libcp1plugin.cc b/libcc1/libcp1plugin.cc
index 83dab7f58b1..e2d5039a0a1 100644
--- a/libcc1/libcp1plugin.cc
+++ b/libcc1/libcp1plugin.cc
@@ -34,6 +34,8 @@
#define INCLUDE_MEMORY
#define INCLUDE_VECTOR
+#define INCLUDE_UNIQUE_PTR
+
#include "gcc-plugin.h"
#include "system.h"
#include "coretypes.h"
--
2.42.0

2
patches/gcc-12.4.0/0004-static-pie.diff
View File

@ -80,7 +80,7 @@ index 3c81c5798d8..cd96eac5d12 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

2
patches/gcc-13.3.0/0004-static-pie.diff
View File

@ -80,7 +80,7 @@ index 3c81c5798d8..cd96eac5d12 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

2
patches/gcc-14.2.0/0004-static-pie.diff
View File

@ -80,7 +80,7 @@ index 3c81c5798d8..cd96eac5d12 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

54
patches/gcc-14.2.0/0010-ppc64-quadmath-pr116007.diff Normal file
View File

@ -0,0 +1,54 @@
From 3fe5720430a9ba61ed7562aac4d758cc77d49a28 Mon Sep 17 00:00:00 2001
From: Jakub Jelinek <jakub@redhat.com>
Date: Sat, 3 Aug 2024 20:37:54 +0200
Subject: libquadmath: Fix up libquadmath/math/sqrtq.c compilation in some
powerpc* configurations [PR116007]
My PR114623 change started using soft-fp.h and quad.h for the sqrtq implementation.
Unfortunately, that seems to fail building in some powerpc* configurations, where
TFmode isn't available.
quad.h has:
#ifndef TFtype
typedef float TFtype __attribute__ ((mode (TF)));
#endif
and uses TFtype. quad.h has:
/* Define the complex type corresponding to __float128
("_Complex __float128" is not allowed) */
#if (!defined(_ARCH_PPC)) || defined(__LONG_DOUBLE_IEEE128__)
typedef _Complex float __attribute__((mode(TC))) __complex128;
#else
typedef _Complex float __attribute__((mode(KC))) __complex128;
#endif
with the conditional and KCmode use added during porting of libquadmath
to powerpc*, so I've just defined TFtype for powerpc when __LONG_DOUBLE_IEEE128__
isn't defined; I could define it to float __attribute__ ((mode (KF))) but it
seemed easier to just define it to __float128 which should do the same thing.
2024-08-03 Jakub Jelinek <jakub@redhat.com>
PR target/116007
* math/sqrtq.c (TFtype): For PowerPC without __LONG_DOUBLE_IEEE128__
define to __float128 before including soft-fp.h and quad.h.
(cherry picked from commit 3ac02e67503ccffa3dfeeffc0a60fce6bdaca43b)
---
libquadmath/math/sqrtq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/libquadmath/math/sqrtq.c b/libquadmath/math/sqrtq.c
index 8ca2828d42ce..a58998a06670 100644
--- a/libquadmath/math/sqrtq.c
+++ b/libquadmath/math/sqrtq.c
@@ -9,6 +9,9 @@
&& defined(FE_TOWARDZERO) \
&& defined(FE_INEXACT)
#define USE_SOFT_FP 1
+#if defined(_ARCH_PPC) && !defined(__LONG_DOUBLE_IEEE128__)
+#define TFtype __float128
+#endif
#include "../../libgcc/soft-fp/soft-fp.h"
#include "../../libgcc/soft-fp/quad.h"
#endif
--
cgit

14
patches/gcc-14.3.0/0001-ssp_nonshared.diff Normal file
View File

@ -0,0 +1,14 @@
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
index 7837553958b..3c81c5798d8 100644
--- a/gcc/gcc.cc
+++ b/gcc/gcc.cc
@@ -980,7 +980,8 @@ proper position among the other output files. */
#ifndef LINK_SSP_SPEC
#ifdef TARGET_LIBC_PROVIDES_SSP
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
- "|fstack-protector-strong|fstack-protector-explicit:}"
+ "|fstack-protector-strong|fstack-protector-explicit" \
+ ":-lssp_nonshared}"
#else
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
"|fstack-protector-strong|fstack-protector-explicit" \

30
patches/gcc-14.3.0/0002-posix_memalign.diff Normal file
View File

@ -0,0 +1,30 @@
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
index 1b0bfe37852..d7b2b19bb3c 100644
--- a/gcc/config/i386/pmm_malloc.h
+++ b/gcc/config/i386/pmm_malloc.h
@@ -27,12 +27,13 @@
#include <stdlib.h>
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
- may not be visible. */
+ may not be visible and we can't pollute the namespace either. */
#ifndef __cplusplus
-extern int posix_memalign (void **, size_t, size_t);
+extern int _mm_posix_memalign (void **, size_t, size_t)
#else
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
#endif
+__asm__("posix_memalign");
static __inline void *
_mm_malloc (size_t __size, size_t __alignment)
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
return malloc (__size);
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
__alignment = sizeof (void *);
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
return __ptr;
else
return NULL;

346
patches/gcc-14.3.0/0003-j2.diff Normal file
View File

@ -0,0 +1,346 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 357b0bed067..528add999f2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -556,7 +556,7 @@ s390*-*-*)
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
;;
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
-sh[123456789lbe]*-*-* | sh-*-*)
+sh[123456789lbej]*-*-* | sh-*-*)
cpu_type=sh
extra_options="${extra_options} fused-madd.opt"
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*)
extra_options="${extra_options} s390/tpf.opt"
tmake_file="${tmake_file} s390/t-s390"
;;
-sh-*-elf* | sh[12346l]*-*-elf* | \
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
+sh-*-elf* | sh[12346lj]*-*-elf* | \
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
if test x${with_endian} = x; then
case ${target} in
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
shbe-*-* | sheb-*-*) with_endian=big,little ;;
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
shl* | sh*-*-linux* | \
sh-superh-elf) with_endian=little,big ;;
- sh[1234]*-*-*) with_endian=big ;;
+ sh[j1234]*-*-*) with_endian=big ;;
*) with_endian=big,little ;;
esac
fi
@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
sh2a*) sh_cpu_target=sh2a ;;
sh2e*) sh_cpu_target=sh2e ;;
+ shj2*) sh_cpu_target=shj2;;
sh2*) sh_cpu_target=sh2 ;;
*) sh_cpu_target=sh1 ;;
esac
@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
"") sh_cpu_default=${sh_cpu_target} ;;
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
esac
@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
case ${target} in
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
esac
if test x$with_fp = xno; then
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
m1 | m2 | m2e | m3 | m3e | \
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
+ mj2)
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
# It is passed to MULTIILIB_OPTIONS verbatim.
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
if test x${enable_incomplete_targets} = xyes ; then
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
fi
tm_file="$tm_file ./sysroot-suffix.h"
tmake_file="$tmake_file t-sysroot-suffix"
@@ -5175,6 +5177,8 @@ case "${target}" in
;;
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
;;
+ mj2)
+ ;;
*)
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
@@ -5385,7 +5389,7 @@ case ${target} in
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
;;
- sh[123456ble]*-*-* | sh-*-*)
+ sh[123456blej]*-*-* | sh-*-*)
c_target_objs="${c_target_objs} sh-c.o"
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index 1564109c942..798c1c1c1a3 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
model_names[sh_atomic_model::soft_imask] = "soft-imask";
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
const char* model_cdef_names[sh_atomic_model::num_models];
model_cdef_names[sh_atomic_model::none] = "NONE";
@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
sh_atomic_model ret;
ret.type = sh_atomic_model::none;
@@ -771,6 +773,9 @@ got_mode_name:;
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
err_ret ("cannot use atomic model %s in user mode", ret.name);
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
+
return ret;
#undef err_ret
@@ -827,6 +832,8 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH2E;
if (TARGET_SH2A)
sh_cpu = PROCESSOR_SH2A;
+ if (TARGET_SHJ2)
+ sh_cpu = PROCESSOR_SHJ2;
if (TARGET_SH3)
sh_cpu = PROCESSOR_SH3;
if (TARGET_SH3E)
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index d2280e2ffe6..3a54a896721 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
+#define SUPPORT_SHJ2 1
#endif
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
+#define SUPPORT_SHJ2 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
- | MASK_FPU_SINGLE_ONLY)
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
/* This defaults us to big-endian. */
#ifndef TARGET_ENDIAN_DEFAULT
@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
-%{m4al:-dsp}"
+%{m4al:-dsp} \
+%{mj2:-isa=j2}"
#define ASM_SPEC SH_ASM_SPEC
@@ -347,6 +351,7 @@ struct sh_atomic_model
hard_llcs,
soft_tcb,
soft_imask,
+ hard_cas,
num_models
};
@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
#define TARGET_ATOMIC_SOFT_IMASK \
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
+#define TARGET_ATOMIC_HARD_CAS \
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
+
#endif // __cplusplus
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
/* Nonzero if the target supports dynamic shift instructions
like shad and shld. */
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
/* The cost of using the dynamic shift insns (shad, shld) are the same
if they are available. If they are not available a library function will
@@ -1747,6 +1755,7 @@ enum processor_type {
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
+ PROCESSOR_SHJ2,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index b4755a812f3..0989a1c18da 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -65,6 +65,10 @@ m2e
Target RejectNegative Condition(SUPPORT_SH2E)
Generate SH2e code.
+mj2
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
+Generate J2 code.
+
m3
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
Generate SH3 code.
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index 2b43f8edb86..118fc5d06db 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -240,6 +240,9 @@
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
exp_val, new_val);
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
+ exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
exp_val, new_val);
@@ -306,6 +309,57 @@
}
[(set_attr "length" "14")])
+(define_expand "atomic_compare_and_swapsi_cas"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{
+ rtx mem = gen_rtx_REG (SImode, 0);
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
+ DONE;
+})
+
+(define_insn "shj2_cas"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "=r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CMPXCHG_1))
+ (set (reg:SI T_REG)
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
+ "TARGET_ATOMIC_HARD_CAS"
+ "cas.l %2,%0,@%1"
+ [(set_attr "length" "2")]
+)
+
+(define_expand "atomic_compare_and_swapqi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
+(define_expand "atomic_compare_and_swaphi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
;; The QIHImode llcs patterns modify the address register of the memory
;; operand. In order to express that, we have to open code the memory
;; operand. Initially the insn is expanded like every other atomic insn
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
index 888f8ff7f25..29fd6ae45fd 100644
--- a/gcc/config/sh/t-sh
+++ b/gcc/config/sh/t-sh
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
m2a-single,m2a-single-only \
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
- m4,m4-100,m4-200,m4-300,m4a; do \
+ m4,m4-100,m4-200,m4-300,m4a \
+ mj2; do \
subst= ; \
for lib in `echo $$abi|tr , ' '` ; do \
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
# SH1 and SH2A support big endian only.
ifeq ($(DEFAULT_ENDIAN),ml)
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
else
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
endif
MULTILIB_OSDIRNAMES = \
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
+ mj2=!j2
$(out_object_file): gt-sh.h
gt-sh.h : s-gtype ; @true

92
patches/gcc-14.3.0/0004-static-pie.diff Normal file
View File

@ -0,0 +1,92 @@
diff --git a/gcc/common.opt b/gcc/common.opt
index a75b44ee47e..7c564818b49 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -3473,11 +3473,11 @@ Driver
no-pie
Driver RejectNegative Negative(shared)
-Don't create a dynamically linked position independent executable.
+Don't create a position independent executable.
pie
Driver RejectNegative Negative(no-pie)
-Create a dynamically linked position independent executable.
+Create a position independent executable.
static-pie
Driver RejectNegative Negative(pie)
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index 5ebbf42a13d..bb907d8e89a 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define GNU_USER_TARGET_STARTFILE_SPEC \
"%{shared:; \
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
- static:crt1.o%s; \
- static-pie:rcrt1.o%s; \
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
" PIE_SPEC ":Scrt1.o%s; \
:crt1.o%s} " \
GNU_USER_TARGET_CRTI " \
- %{static:crtbeginT.o%s; \
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
+ static:crtbeginT.o%s; \
:crtbegin.o%s} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
GNU userspace "finalizer" file, `crtn.o'. */
#define GNU_USER_TARGET_ENDFILE_SPEC \
- "%{!static:%{fvtable-verify=none:%s; \
+ "%{static|static-pie:; \
+ fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
- fvtable-verify=std:vtv_end.o%s}} \
- %{static:crtend.o%s; \
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
+ fvtable-verify=std:vtv_end.o%s} \
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
:crtend.o%s} " \
GNU_USER_TARGET_CRTN " " \
CRTOFFLOADEND
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
#if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
#endif
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
index 3c81c5798d8..cd96eac5d12 100644
--- a/gcc/gcc.cc
+++ b/gcc/gcc.cc
@@ -1010,7 +1010,7 @@ proper position among the other output files. */
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
#else
-#define PIE_SPEC "pie"
+#define PIE_SPEC "pie|static-pie"
#define FPIE1_SPEC "fpie"
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
#define FPIE2_SPEC "fPIE"
@@ -1034,12 +1034,12 @@ proper position among the other output files. */
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""
#endif
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
#endif
#ifndef LINK_BUILDID_SPEC

20
patches/gcc-14.3.0/0005-m68k-sqrt.diff Normal file
View File

@ -0,0 +1,20 @@
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 59a456cd496..dbfddea41bd 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -4174,13 +4174,13 @@
(define_expand "sqrt<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "")
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
"")
(define_insn "sqrt<mode>2_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
- "TARGET_68881"
+ "TARGET_68881 && TARGET_68040"
{
if (FP_REG_P (operands[1]))
return "f<FP:round>sqrt%.x %1,%0";

8
patches/gcc-14.3.0/0006-cow-libstdc++v3.diff Normal file
View File

@ -0,0 +1,8 @@
--- a/libstdc++-v3/ChangeLog 2024-03-13 18:04:21.050801063 -0400
+++ b/libstdc++-v3/ChangeLog 2024-03-13 18:04:25.665836804 -0400
@@ -4068,4 +4068,4 @@
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
-notice and this notice are preserved.
+notice and this notice are preserved.

11
patches/gcc-14.3.0/0007-fdpic-unwind.diff Normal file
View File

@ -0,0 +1,11 @@
--- a/libgcc/unwind-pe.h 2024-03-14 05:59:53.754073149 +0900
+++ b/libgcc/unwind-pe.h 2024-03-14 06:00:41.226074492 +0900
@@ -262,7 +262,7 @@
if (result != 0)
{
-#if __FDPIC__
+#if __FDPIC__ && __arm__
/* FDPIC relative addresses imply taking the GOT address
into account. */
if ((encoding & DW_EH_PE_pcrel) && (encoding & DW_EH_PE_indirect))

38
patches/gcc-14.3.0/0008-fdpic-crtstuff-pr114158.diff Normal file
View File

@ -0,0 +1,38 @@
--- a/libgcc/crtstuff.c 2023-05-29 17:46:32.000000000 +0900
+++ b/libgcc/crtstuff.c 2024-03-14 06:03:42.398079615 +0900
@@ -441,17 +441,9 @@
#ifdef FINI_SECTION_ASM_OP
CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
#elif defined (FINI_ARRAY_SECTION_ASM_OP)
-#if defined(__FDPIC__)
-__asm__("\t.equ\t__do_global_dtors_aux_alias, __do_global_dtors_aux\n");
-extern char __do_global_dtors_aux_alias;
-static void *__do_global_dtors_aux_fini_array_entry[]
-__attribute__ ((__used__, section(".fini_array"), aligned(sizeof(void *))))
- = { &__do_global_dtors_aux_alias };
-#else /* defined(__FDPIC__) */
static func_ptr __do_global_dtors_aux_fini_array_entry[]
__attribute__ ((__used__, section(".fini_array"),
aligned(__alignof__(func_ptr)))) = { __do_global_dtors_aux };
-#endif /* defined(__FDPIC__) */
#else /* !FINI_SECTION_ASM_OP && !FINI_ARRAY_SECTION_ASM_OP */
static void __attribute__((used))
__do_global_dtors_aux_1 (void)
@@ -494,17 +486,9 @@
#ifdef __LIBGCC_INIT_SECTION_ASM_OP__
CRT_CALL_STATIC_FUNCTION (__LIBGCC_INIT_SECTION_ASM_OP__, frame_dummy)
#else /* defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
-#if defined(__FDPIC__)
-__asm__("\t.equ\t__frame_dummy_alias, frame_dummy\n");
-extern char __frame_dummy_alias;
-static void *__frame_dummy_init_array_entry[]
-__attribute__ ((__used__, section(".init_array"), aligned(sizeof(void *))))
- = { &__frame_dummy_alias };
-#else /* defined(__FDPIC__) */
static func_ptr __frame_dummy_init_array_entry[]
__attribute__ ((__used__, section(".init_array"),
aligned(__alignof__(func_ptr)))) = { frame_dummy };
-#endif /* defined(__FDPIC__) */
#endif /* !defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
#endif /* USE_EH_FRAME_REGISTRY || USE_TM_CLONE_REGISTRY */

12
patches/gcc-14.3.0/0009-sh-fdpic-pr114641.diff Normal file
View File

@ -0,0 +1,12 @@
--- gcc-11.4.0/gcc/config/sh/sh.cc.orig 2024-04-04 05:52:42.125373614 +0900
+++ gcc-11.4.0/gcc/config/sh/sh.cc 2024-04-04 22:54:01.875106654 +0900
@@ -9147,7 +9147,7 @@
{
/* Weak functions may be NULL which doesn't work with
GOTOFFFUNCDESC because the runtime offset is not known. */
- if (SYMBOL_REF_WEAK (orig))
+ if (SYMBOL_REF_WEAK (orig) || (TREE_PUBLIC(SYMBOL_REF_DECL(orig)) && DECL_VISIBILITY (SYMBOL_REF_DECL(orig)) != VISIBILITY_HIDDEN))
emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
else
emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));

14
patches/gcc-15.1.0/0001-ssp_nonshared.diff Normal file
View File

@ -0,0 +1,14 @@
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
index 7837553958b..3c81c5798d8 100644
--- a/gcc/gcc.cc
+++ b/gcc/gcc.cc
@@ -980,7 +980,8 @@ proper position among the other output files. */
#ifndef LINK_SSP_SPEC
#ifdef TARGET_LIBC_PROVIDES_SSP
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
- "|fstack-protector-strong|fstack-protector-explicit:}"
+ "|fstack-protector-strong|fstack-protector-explicit" \
+ ":-lssp_nonshared}"
#else
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
"|fstack-protector-strong|fstack-protector-explicit" \

30
patches/gcc-15.1.0/0002-posix_memalign.diff Normal file
View File

@ -0,0 +1,30 @@
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
index 1b0bfe37852..d7b2b19bb3c 100644
--- a/gcc/config/i386/pmm_malloc.h
+++ b/gcc/config/i386/pmm_malloc.h
@@ -27,12 +27,13 @@
#include <stdlib.h>
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
- may not be visible. */
+ may not be visible and we can't pollute the namespace either. */
#ifndef __cplusplus
-extern int posix_memalign (void **, size_t, size_t);
+extern int _mm_posix_memalign (void **, size_t, size_t)
#else
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
#endif
+__asm__("posix_memalign");
static __inline void *
_mm_malloc (size_t __size, size_t __alignment)
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
return malloc (__size);
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
__alignment = sizeof (void *);
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
return __ptr;
else
return NULL;

346
patches/gcc-15.1.0/0003-j2.diff Normal file
View File

@ -0,0 +1,346 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 357b0bed067..528add999f2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -556,7 +556,7 @@ s390*-*-*)
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
;;
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
-sh[123456789lbe]*-*-* | sh-*-*)
+sh[123456789lbej]*-*-* | sh-*-*)
cpu_type=sh
extra_options="${extra_options} fused-madd.opt"
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*)
extra_options="${extra_options} s390/tpf.opt"
tmake_file="${tmake_file} s390/t-s390"
;;
-sh-*-elf* | sh[12346l]*-*-elf* | \
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
+sh-*-elf* | sh[12346lj]*-*-elf* | \
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
if test x${with_endian} = x; then
case ${target} in
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
shbe-*-* | sheb-*-*) with_endian=big,little ;;
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
shl* | sh*-*-linux* | \
sh-superh-elf) with_endian=little,big ;;
- sh[1234]*-*-*) with_endian=big ;;
+ sh[j1234]*-*-*) with_endian=big ;;
*) with_endian=big,little ;;
esac
fi
@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
sh2a*) sh_cpu_target=sh2a ;;
sh2e*) sh_cpu_target=sh2e ;;
+ shj2*) sh_cpu_target=shj2;;
sh2*) sh_cpu_target=sh2 ;;
*) sh_cpu_target=sh1 ;;
esac
@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
"") sh_cpu_default=${sh_cpu_target} ;;
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
esac
@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
case ${target} in
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
esac
if test x$with_fp = xno; then
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
m1 | m2 | m2e | m3 | m3e | \
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
+ mj2)
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
# It is passed to MULTIILIB_OPTIONS verbatim.
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
if test x${enable_incomplete_targets} = xyes ; then
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
fi
tm_file="$tm_file ./sysroot-suffix.h"
tmake_file="$tmake_file t-sysroot-suffix"
@@ -5175,6 +5177,8 @@ case "${target}" in
;;
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
;;
+ mj2)
+ ;;
*)
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
@@ -5385,7 +5389,7 @@ case ${target} in
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
;;
- sh[123456ble]*-*-* | sh-*-*)
+ sh[123456blej]*-*-* | sh-*-*)
c_target_objs="${c_target_objs} sh-c.o"
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
index 1564109c942..798c1c1c1a3 100644
--- a/gcc/config/sh/sh.cc
+++ b/gcc/config/sh/sh.cc
@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
model_names[sh_atomic_model::soft_imask] = "soft-imask";
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
const char* model_cdef_names[sh_atomic_model::num_models];
model_cdef_names[sh_atomic_model::none] = "NONE";
@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
sh_atomic_model ret;
ret.type = sh_atomic_model::none;
@@ -771,6 +773,9 @@ got_mode_name:;
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
err_ret ("cannot use atomic model %s in user mode", ret.name);
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
+
return ret;
#undef err_ret
@@ -827,6 +832,8 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH2E;
if (TARGET_SH2A)
sh_cpu = PROCESSOR_SH2A;
+ if (TARGET_SHJ2)
+ sh_cpu = PROCESSOR_SHJ2;
if (TARGET_SH3)
sh_cpu = PROCESSOR_SH3;
if (TARGET_SH3E)
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index d2280e2ffe6..3a54a896721 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
+#define SUPPORT_SHJ2 1
#endif
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
+#define SUPPORT_SHJ2 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
- | MASK_FPU_SINGLE_ONLY)
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
/* This defaults us to big-endian. */
#ifndef TARGET_ENDIAN_DEFAULT
@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
-%{m4al:-dsp}"
+%{m4al:-dsp} \
+%{mj2:-isa=j2}"
#define ASM_SPEC SH_ASM_SPEC
@@ -347,6 +351,7 @@ struct sh_atomic_model
hard_llcs,
soft_tcb,
soft_imask,
+ hard_cas,
num_models
};
@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
#define TARGET_ATOMIC_SOFT_IMASK \
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
+#define TARGET_ATOMIC_HARD_CAS \
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
+
#endif // __cplusplus
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
/* Nonzero if the target supports dynamic shift instructions
like shad and shld. */
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
/* The cost of using the dynamic shift insns (shad, shld) are the same
if they are available. If they are not available a library function will
@@ -1747,6 +1755,7 @@ enum processor_type {
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
+ PROCESSOR_SHJ2,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index b4755a812f3..0989a1c18da 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -65,6 +65,10 @@ m2e
Target RejectNegative Condition(SUPPORT_SH2E)
Generate SH2e code.
+mj2
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
+Generate J2 code.
+
m3
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
Generate SH3 code.
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index 2b43f8edb86..118fc5d06db 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -240,6 +240,9 @@
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
exp_val, new_val);
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
+ exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
exp_val, new_val);
@@ -306,6 +309,57 @@
}
[(set_attr "length" "14")])
+(define_expand "atomic_compare_and_swapsi_cas"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{
+ rtx mem = gen_rtx_REG (SImode, 0);
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
+ DONE;
+})
+
+(define_insn "shj2_cas"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "=r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CMPXCHG_1))
+ (set (reg:SI T_REG)
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
+ "TARGET_ATOMIC_HARD_CAS"
+ "cas.l %2,%0,@%1"
+ [(set_attr "length" "2")]
+)
+
+(define_expand "atomic_compare_and_swapqi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
+(define_expand "atomic_compare_and_swaphi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
;; The QIHImode llcs patterns modify the address register of the memory
;; operand. In order to express that, we have to open code the memory
;; operand. Initially the insn is expanded like every other atomic insn
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
index 888f8ff7f25..29fd6ae45fd 100644
--- a/gcc/config/sh/t-sh
+++ b/gcc/config/sh/t-sh
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
m2a-single,m2a-single-only \
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
- m4,m4-100,m4-200,m4-300,m4a; do \
+ m4,m4-100,m4-200,m4-300,m4a \
+ mj2; do \
subst= ; \
for lib in `echo $$abi|tr , ' '` ; do \
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
# SH1 and SH2A support big endian only.
ifeq ($(DEFAULT_ENDIAN),ml)
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
else
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
endif
MULTILIB_OSDIRNAMES = \
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
+ mj2=!j2
$(out_object_file): gt-sh.h
gt-sh.h : s-gtype ; @true

92
patches/gcc-15.1.0/0004-static-pie.diff Normal file
View File

@ -0,0 +1,92 @@
diff --git a/gcc/common.opt b/gcc/common.opt
index a75b44ee47e..7c564818b49 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -3473,11 +3473,11 @@ Driver
no-pie
Driver RejectNegative Negative(shared)
-Don't create a dynamically linked position independent executable.
+Don't create a position independent executable.
pie
Driver RejectNegative Negative(no-pie)
-Create a dynamically linked position independent executable.
+Create a position independent executable.
static-pie
Driver RejectNegative Negative(pie)
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index 5ebbf42a13d..bb907d8e89a 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define GNU_USER_TARGET_STARTFILE_SPEC \
"%{shared:; \
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
- static:crt1.o%s; \
- static-pie:rcrt1.o%s; \
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
" PIE_SPEC ":Scrt1.o%s; \
:crt1.o%s} " \
GNU_USER_TARGET_CRTI " \
- %{static:crtbeginT.o%s; \
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
+ static:crtbeginT.o%s; \
:crtbegin.o%s} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
GNU userspace "finalizer" file, `crtn.o'. */
#define GNU_USER_TARGET_ENDFILE_SPEC \
- "%{!static:%{fvtable-verify=none:%s; \
+ "%{static|static-pie:; \
+ fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
- fvtable-verify=std:vtv_end.o%s}} \
- %{static:crtend.o%s; \
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
+ fvtable-verify=std:vtv_end.o%s} \
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
:crtend.o%s} " \
GNU_USER_TARGET_CRTN " " \
CRTOFFLOADEND
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
#if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
#endif
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
index 3c81c5798d8..cd96eac5d12 100644
--- a/gcc/gcc.cc
+++ b/gcc/gcc.cc
@@ -1010,7 +1010,7 @@ proper position among the other output files. */
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
#else
-#define PIE_SPEC "pie"
+#define PIE_SPEC "pie|static-pie"
#define FPIE1_SPEC "fpie"
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
#define FPIE2_SPEC "fPIE"
@@ -1034,12 +1034,12 @@ proper position among the other output files. */
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""
#endif
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
#endif
#ifndef LINK_BUILDID_SPEC

20
patches/gcc-15.1.0/0005-m68k-sqrt.diff Normal file
View File

@ -0,0 +1,20 @@
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 59a456cd496..dbfddea41bd 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -4174,13 +4174,13 @@
(define_expand "sqrt<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "")
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
"")
(define_insn "sqrt<mode>2_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
- "TARGET_68881"
+ "TARGET_68881 && TARGET_68040"
{
if (FP_REG_P (operands[1]))
return "f<FP:round>sqrt%.x %1,%0";

8
patches/gcc-15.1.0/0006-cow-libstdc++v3.diff Normal file
View File

@ -0,0 +1,8 @@
--- a/libstdc++-v3/ChangeLog 2024-03-13 18:04:21.050801063 -0400
+++ b/libstdc++-v3/ChangeLog 2024-03-13 18:04:25.665836804 -0400
@@ -4068,4 +4068,4 @@
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
-notice and this notice are preserved.
+notice and this notice are preserved.

11
patches/gcc-15.1.0/0007-fdpic-unwind.diff Normal file
View File

@ -0,0 +1,11 @@
--- a/libgcc/unwind-pe.h 2024-03-14 05:59:53.754073149 +0900
+++ b/libgcc/unwind-pe.h 2024-03-14 06:00:41.226074492 +0900
@@ -262,7 +262,7 @@
if (result != 0)
{
-#if __FDPIC__
+#if __FDPIC__ && __arm__
/* FDPIC relative addresses imply taking the GOT address
into account. */
if ((encoding & DW_EH_PE_pcrel) && (encoding & DW_EH_PE_indirect))

38
patches/gcc-15.1.0/0008-fdpic-crtstuff-pr114158.diff Normal file
View File

@ -0,0 +1,38 @@
--- a/libgcc/crtstuff.c 2023-05-29 17:46:32.000000000 +0900
+++ b/libgcc/crtstuff.c 2024-03-14 06:03:42.398079615 +0900
@@ -441,17 +441,9 @@
#ifdef FINI_SECTION_ASM_OP
CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
#elif defined (FINI_ARRAY_SECTION_ASM_OP)
-#if defined(__FDPIC__)
-__asm__("\t.equ\t__do_global_dtors_aux_alias, __do_global_dtors_aux\n");
-extern char __do_global_dtors_aux_alias;
-static void *__do_global_dtors_aux_fini_array_entry[]
-__attribute__ ((__used__, section(".fini_array"), aligned(sizeof(void *))))
- = { &__do_global_dtors_aux_alias };
-#else /* defined(__FDPIC__) */
static func_ptr __do_global_dtors_aux_fini_array_entry[]
__attribute__ ((__used__, section(".fini_array"),
aligned(__alignof__(func_ptr)))) = { __do_global_dtors_aux };
-#endif /* defined(__FDPIC__) */
#else /* !FINI_SECTION_ASM_OP && !FINI_ARRAY_SECTION_ASM_OP */
static void __attribute__((used))
__do_global_dtors_aux_1 (void)
@@ -494,17 +486,9 @@
#ifdef __LIBGCC_INIT_SECTION_ASM_OP__
CRT_CALL_STATIC_FUNCTION (__LIBGCC_INIT_SECTION_ASM_OP__, frame_dummy)
#else /* defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
-#if defined(__FDPIC__)
-__asm__("\t.equ\t__frame_dummy_alias, frame_dummy\n");
-extern char __frame_dummy_alias;
-static void *__frame_dummy_init_array_entry[]
-__attribute__ ((__used__, section(".init_array"), aligned(sizeof(void *))))
- = { &__frame_dummy_alias };
-#else /* defined(__FDPIC__) */
static func_ptr __frame_dummy_init_array_entry[]
__attribute__ ((__used__, section(".init_array"),
aligned(__alignof__(func_ptr)))) = { frame_dummy };
-#endif /* defined(__FDPIC__) */
#endif /* !defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
#endif /* USE_EH_FRAME_REGISTRY || USE_TM_CLONE_REGISTRY */

12
patches/gcc-15.1.0/0009-sh-fdpic-pr114641.diff Normal file
View File

@ -0,0 +1,12 @@
--- gcc-11.4.0/gcc/config/sh/sh.cc.orig 2024-04-04 05:52:42.125373614 +0900
+++ gcc-11.4.0/gcc/config/sh/sh.cc 2024-04-04 22:54:01.875106654 +0900
@@ -9147,7 +9147,7 @@
{
/* Weak functions may be NULL which doesn't work with
GOTOFFFUNCDESC because the runtime offset is not known. */
- if (SYMBOL_REF_WEAK (orig))
+ if (SYMBOL_REF_WEAK (orig) || (TREE_PUBLIC(SYMBOL_REF_DECL(orig)) && DECL_VISIBILITY (SYMBOL_REF_DECL(orig)) != VISIBILITY_HIDDEN))
emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
else
emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));

146
patches/gcc-5.3.0/0025-configsub-sheb.diff Normal file
View File

@ -0,0 +1,146 @@
--- gcc-5.3.0.orig/config.sub
+++ gcc-5.3.0/config.sub
@@ -1,8 +1,8 @@
#! /bin/sh
# Configuration validation subroutine script.
-# Copyright 1992-2015 Free Software Foundation, Inc.
+# Copyright 1992-2016 Free Software Foundation, Inc.
-timestamp='2015-01-01'
+timestamp='2016-03-30'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
# Otherwise, we print the canonical config type on stdout and succeed.
# You can get the latest version of this script from:
-# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD
+# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub
# This file is supposed to be the same for all GNU packages
# and recognize all the CPU types, system types and aliases
@@ -53,8 +53,7 @@
me=`echo "$0" | sed -e 's,.*/,,'`
usage="\
-Usage: $0 [OPTION] CPU-MFR-OPSYS
- $0 [OPTION] ALIAS
+Usage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS
Canonicalize a configuration name.
@@ -68,7 +67,7 @@
version="\
GNU config.sub ($timestamp)
-Copyright 1992-2015 Free Software Foundation, Inc.
+Copyright 1992-2016 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE."
@@ -117,7 +116,7 @@
case $maybe_os in
nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \
linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \
- knetbsd*-gnu* | netbsd*-gnu* | \
+ knetbsd*-gnu* | netbsd*-gnu* | netbsd*-eabi* | \
kopensolaris*-gnu* | \
storm-chaos* | os2-emx* | rtmk-nova*)
os=-$maybe_os
@@ -255,11 +254,12 @@
| arc | arceb \
| arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \
| avr | avr32 \
+ | ba \
| be32 | be64 \
| bfin \
| c4x | c8051 | clipper \
| d10v | d30v | dlx | dsp16xx \
- | epiphany \
+ | e2k | epiphany \
| fido | fr30 | frv | ft32 \
| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
| hexagon \
@@ -305,7 +305,7 @@
| riscv32 | riscv64 \
| rl78 | rx \
| score \
- | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
+ | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[234]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
| sh64 | sh64le \
| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
@@ -376,12 +376,13 @@
| alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \
| arm-* | armbe-* | armle-* | armeb-* | armv*-* \
| avr-* | avr32-* \
+ | ba-* \
| be32-* | be64-* \
| bfin-* | bs2000-* \
| c[123]* | c30-* | [cjt]90-* | c4x-* \
| c8051-* | clipper-* | craynv-* | cydra-* \
| d10v-* | d30v-* | dlx-* \
- | elxsi-* \
+ | e2k-* | elxsi-* \
| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
| h8300-* | h8500-* \
| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
@@ -428,12 +429,13 @@
| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
| pyramid-* \
+ | riscv32-* | riscv64-* \
| rl78-* | romp-* | rs6000-* | rx-* \
| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
| sparclite-* \
- | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \
+ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx*-* \
| tahoe-* \
| tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \
| tile*-* \
@@ -518,6 +520,9 @@
basic_machine=i386-pc
os=-aros
;;
+ asmjs)
+ basic_machine=asmjs-unknown
+ ;;
aux)
basic_machine=m68k-apple
os=-aux
@@ -1373,11 +1378,11 @@
| -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \
| -sym* | -kopensolaris* | -plan9* \
| -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \
- | -aos* | -aros* \
+ | -aos* | -aros* | -cloudabi* | -sortix* \
| -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
| -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
| -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \
- | -bitrig* | -openbsd* | -solidbsd* \
+ | -bitrig* | -openbsd* | -solidbsd* | -libertybsd* \
| -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \
| -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \
| -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
@@ -1393,7 +1398,8 @@
| -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \
| -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \
| -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \
- | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*)
+ | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* \
+ | -onefs* | -tirtos*)
# Remember, each alternative MUST END IN *, to match a version number.
;;
-qnx*)
@@ -1524,6 +1530,8 @@
os=-dicos
;;
-nacl*)
+ ;;
+ -ios)
;;
-none)
;;

2
patches/gcc-6.5.0/0020-static-pie-support.diff
View File

@ -34,7 +34,7 @@ index 0576ea7..0a280e0 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

2
patches/gcc-7.5.0/0010-static-pie-support.diff
View File

@ -53,7 +53,7 @@ index 91eb0534722..74a390e6005 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

2
patches/gcc-8.5.0/0012-static-pie.diff
View File

@ -105,7 +105,7 @@ index eb1610ba8b0..87560afb03c 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static-pie:-static} %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static-pie:-static} %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""

2
patches/gcc-9.4.0/0012-static-pie.diff
View File

@ -74,7 +74,7 @@ index d185c01b257..5d3f81c5fc5 100644
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static-pie:-static} %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic -static}"
#endif
#else
#define LD_PIE_SPEC ""