73 lines
2.6 KiB
C
73 lines
2.6 KiB
C
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//===-- llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h --*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a version of MachineIRBuilder which does trivial
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/// constant folding.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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namespace llvm {
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/// An MIRBuilder which does trivial constant folding of binary ops.
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/// Calls to buildInstr will also try to constant fold binary ops.
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class ConstantFoldingMIRBuilder : public MachineIRBuilder {
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public:
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// Pull in base class constructors.
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using MachineIRBuilder::MachineIRBuilder;
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virtual ~ConstantFoldingMIRBuilder() = default;
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// Try to provide an overload for buildInstr for binary ops in order to
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// constant fold.
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MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
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ArrayRef<SrcOp> SrcOps,
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Optional<unsigned> Flags = None) override {
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switch (Opc) {
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default:
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break;
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case TargetOpcode::G_ADD:
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case TargetOpcode::G_AND:
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case TargetOpcode::G_ASHR:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_MUL:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_SHL:
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case TargetOpcode::G_SUB:
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case TargetOpcode::G_XOR:
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case TargetOpcode::G_UDIV:
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case TargetOpcode::G_SDIV:
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case TargetOpcode::G_UREM:
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case TargetOpcode::G_SREM: {
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assert(DstOps.size() == 1 && "Invalid dst ops");
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assert(SrcOps.size() == 2 && "Invalid src ops");
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const DstOp &Dst = DstOps[0];
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const SrcOp &Src0 = SrcOps[0];
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const SrcOp &Src1 = SrcOps[1];
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if (auto MaybeCst =
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ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI()))
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return buildConstant(Dst, MaybeCst->getSExtValue());
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break;
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}
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case TargetOpcode::G_SEXT_INREG: {
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assert(DstOps.size() == 1 && "Invalid dst ops");
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assert(SrcOps.size() == 2 && "Invalid src ops");
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const DstOp &Dst = DstOps[0];
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const SrcOp &Src0 = SrcOps[0];
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const SrcOp &Src1 = SrcOps[1];
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if (auto MaybeCst =
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ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
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return buildConstant(Dst, MaybeCst->getSExtValue());
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break;
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}
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}
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return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps);
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}
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};
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} // namespace llvm
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