55 lines
2.0 KiB
C++
55 lines
2.0 KiB
C++
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//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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using namespace llvm;
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bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
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const MCRegisterInfo &RI) const {
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if (isBranch() || isCall() || isReturn() || isIndirectBranch())
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return true;
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unsigned PC = RI.getProgramCounter();
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if (PC == 0)
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return false;
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if (hasDefOfPhysReg(MI, PC, RI))
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return true;
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return false;
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}
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bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
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const MCRegisterInfo *MRI) const {
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if (const MCPhysReg *ImpDefs = ImplicitDefs)
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for (; *ImpDefs; ++ImpDefs)
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if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
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return true;
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return false;
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}
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bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
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const MCRegisterInfo &RI) const {
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for (int i = 0, e = NumDefs; i != e; ++i)
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if (MI.getOperand(i).isReg() &&
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RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
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return true;
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if (variadicOpsAreDefs())
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for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
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if (MI.getOperand(i).isReg() &&
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RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
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return true;
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return hasImplicitDefOfPhysReg(Reg, &RI);
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}
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