314 lines
12 KiB
C++
314 lines
12 KiB
C++
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//=== ARMCallingConv.cpp - ARM Custom CC Routines ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the custom routines for the ARM Calling Convention that
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// aren't done by tablegen, and includes the table generated implementations.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMCallingConv.h"
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#include "ARMSubtarget.h"
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#include "ARMRegisterInfo.h"
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using namespace llvm;
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// APCS f64 is in register pairs, possibly split to stack
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static bool f64AssignAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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CCState &State, bool CanFail) {
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static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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// Try to get the first register.
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if (unsigned Reg = State.AllocateReg(RegList))
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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else {
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// For the 2nd half of a v2f64, do not fail.
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if (CanFail)
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return false;
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// Put the whole thing on the stack.
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State.addLoc(CCValAssign::getCustomMem(
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ValNo, ValVT, State.AllocateStack(8, Align(4)), LocVT, LocInfo));
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return true;
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}
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// Try to get the second register.
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if (unsigned Reg = State.AllocateReg(RegList))
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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else
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State.addLoc(CCValAssign::getCustomMem(
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ValNo, ValVT, State.AllocateStack(4, Align(4)), LocVT, LocInfo));
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return true;
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}
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static bool CC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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return false;
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if (LocVT == MVT::v2f64 &&
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!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
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return false;
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return true; // we handled it
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}
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// AAPCS f64 is in aligned register pairs
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static bool f64AssignAAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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CCState &State, bool CanFail) {
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static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
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static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
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static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
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static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
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if (Reg == 0) {
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// If we had R3 unallocated only, now we still must to waste it.
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Reg = State.AllocateReg(GPRArgRegs);
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assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
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// For the 2nd half of a v2f64, do not just fail.
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if (CanFail)
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return false;
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// Put the whole thing on the stack.
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State.addLoc(CCValAssign::getCustomMem(
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ValNo, ValVT, State.AllocateStack(8, Align(8)), LocVT, LocInfo));
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return true;
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}
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unsigned i;
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for (i = 0; i < 2; ++i)
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if (HiRegList[i] == Reg)
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break;
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unsigned T = State.AllocateReg(LoRegList[i]);
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(void)T;
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assert(T == LoRegList[i] && "Could not allocate register");
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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static bool CC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
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return false;
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if (LocVT == MVT::v2f64 &&
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!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
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return false;
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return true; // we handled it
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}
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static bool f64RetAssign(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo, CCState &State) {
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static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
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static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
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unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
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if (Reg == 0)
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return false; // we didn't handle it
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unsigned i;
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for (i = 0; i < 2; ++i)
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if (HiRegList[i] == Reg)
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break;
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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static bool RetCC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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return false;
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if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
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return false;
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return true; // we handled it
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}
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static bool RetCC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
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State);
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}
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static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
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ARM::S4, ARM::S5, ARM::S6, ARM::S7,
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ARM::S8, ARM::S9, ARM::S10, ARM::S11,
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ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
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static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
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// Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
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// has InConsecutiveRegs set, and that the last member also has
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// InConsecutiveRegsLast set. We must process all members of the HA before
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// we can allocate it, as we need to know the total number of registers that
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// will be needed in order to (attempt to) allocate a contiguous block.
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static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT,
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MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
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// AAPCS HFAs must have 1-4 elements, all of the same type
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if (PendingMembers.size() > 0)
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assert(PendingMembers[0].getLocVT() == LocVT);
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// Add the argument to the list to be allocated once we know the size of the
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// aggregate. Store the type's required alignment as extra info for later: in
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// the [N x i64] case all trace has been removed by the time we actually get
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// to do allocation.
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PendingMembers.push_back(CCValAssign::getPending(
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ValNo, ValVT, LocVT, LocInfo, ArgFlags.getNonZeroOrigAlign().value()));
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if (!ArgFlags.isInConsecutiveRegsLast())
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return true;
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// Try to allocate a contiguous block of registers, each of the correct
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// size to hold one member.
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auto &DL = State.getMachineFunction().getDataLayout();
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const Align StackAlign = DL.getStackAlignment();
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const Align FirstMemberAlign(PendingMembers[0].getExtraInfo());
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Align Alignment = std::min(FirstMemberAlign, StackAlign);
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ArrayRef<MCPhysReg> RegList;
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switch (LocVT.SimpleTy) {
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case MVT::i32: {
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RegList = RRegList;
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unsigned RegIdx = State.getFirstUnallocated(RegList);
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// First consume all registers that would give an unaligned object. Whether
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// we go on stack or in regs, no-one will be using them in future.
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unsigned RegAlign = alignTo(Alignment.value(), 4) / 4;
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while (RegIdx % RegAlign != 0 && RegIdx < RegList.size())
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State.AllocateReg(RegList[RegIdx++]);
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break;
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}
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case MVT::f16:
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case MVT::bf16:
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case MVT::f32:
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RegList = SRegList;
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break;
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case MVT::v4f16:
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case MVT::v4bf16:
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case MVT::f64:
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RegList = DRegList;
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break;
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case MVT::v8f16:
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case MVT::v8bf16:
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case MVT::v2f64:
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RegList = QRegList;
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break;
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default:
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llvm_unreachable("Unexpected member type for block aggregate");
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break;
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}
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unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
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if (RegResult) {
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for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin();
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It != PendingMembers.end(); ++It) {
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It->convertToReg(RegResult);
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State.addLoc(*It);
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++RegResult;
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}
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PendingMembers.clear();
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return true;
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}
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// Register allocation failed, we'll be needing the stack
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unsigned Size = LocVT.getSizeInBits() / 8;
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if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) {
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// If nothing else has used the stack until this point, a non-HFA aggregate
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// can be split between regs and stack.
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unsigned RegIdx = State.getFirstUnallocated(RegList);
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for (auto &It : PendingMembers) {
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if (RegIdx >= RegList.size())
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It.convertToMem(State.AllocateStack(Size, Align(Size)));
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else
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It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
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State.addLoc(It);
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}
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PendingMembers.clear();
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return true;
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} else if (LocVT != MVT::i32)
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RegList = SRegList;
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// Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core)
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for (auto Reg : RegList)
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State.AllocateReg(Reg);
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// After the first item has been allocated, the rest are packed as tightly as
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// possible. (E.g. an incoming i64 would have starting Align of 8, but we'll
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// be allocating a bunch of i32 slots).
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const Align RestAlign = std::min(Alignment, Align(Size));
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for (auto &It : PendingMembers) {
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It.convertToMem(State.AllocateStack(Size, Alignment));
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State.addLoc(It);
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Alignment = RestAlign;
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}
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// All pending members have now been allocated
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PendingMembers.clear();
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// This will be allocated by the last member of the aggregate
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return true;
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}
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static bool CustomAssignInRegList(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo, CCState &State,
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ArrayRef<MCPhysReg> RegList) {
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unsigned Reg = State.AllocateReg(RegList);
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if (Reg) {
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return true;
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}
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return false;
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}
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static bool CC_ARM_AAPCS_Custom_f16(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State) {
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// f16 arguments are extended to i32 and assigned to a register in [r0, r3]
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return CustomAssignInRegList(ValNo, ValVT, MVT::i32, LocInfo, State,
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RRegList);
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}
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static bool CC_ARM_AAPCS_VFP_Custom_f16(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags,
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CCState &State) {
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// f16 arguments are extended to f32 and assigned to a register in [s0, s15]
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return CustomAssignInRegList(ValNo, ValVT, MVT::f32, LocInfo, State,
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SRegList);
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}
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// Include the table generated calling convention implementations.
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#include "ARMGenCallingConv.inc"
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