116 lines
4.2 KiB
C
116 lines
4.2 KiB
C
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//===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AVRMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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//
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#ifndef LLVM_AVR_CODE_EMITTER_H
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#define LLVM_AVR_CODE_EMITTER_H
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#include "AVRFixupKinds.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/Support/DataTypes.h"
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#define GET_INSTRINFO_OPERAND_TYPES_ENUM
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#include "AVRGenInstrInfo.inc"
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namespace llvm {
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class MCContext;
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class MCExpr;
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class MCFixup;
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class MCInst;
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class MCInstrInfo;
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class MCOperand;
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class MCSubtargetInfo;
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class raw_ostream;
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/// Writes AVR machine code to a stream.
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class AVRMCCodeEmitter : public MCCodeEmitter {
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public:
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AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
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: MCII(MCII), Ctx(Ctx) {}
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private:
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/// Finishes up encoding an LD/ST instruction.
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/// The purpose of this function is to set an bit in the instruction
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/// which follows no logical pattern. See the implementation for details.
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unsigned loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
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const MCSubtargetInfo &STI) const;
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/// Gets the encoding for a conditional branch target.
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template <AVR::Fixups Fixup>
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unsigned encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Encodes the `PTRREGS` operand to a load or store instruction.
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unsigned encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Encodes a `register+immediate` operand for `LDD`/`STD`.
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unsigned encodeMemri(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Takes the complement of a number (~0 - val).
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unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Encodes an immediate value with a given fixup.
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/// \tparam Offset The offset into the instruction for the fixup.
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template <AVR::Fixups Fixup, unsigned Offset>
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unsigned encodeImm(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Gets the encoding of the target for the `CALL k` instruction.
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unsigned encodeCallTarget(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// TableGen'ed function to get the binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Returns the binary encoding of operand.
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///
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/// If the machine operand requires relocation, the relocation is recorded
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/// and zero is returned.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
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raw_ostream &OS) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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AVRMCCodeEmitter(const AVRMCCodeEmitter &) = delete;
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void operator=(const AVRMCCodeEmitter &) = delete;
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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};
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} // end namespace of llvm.
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#endif // LLVM_AVR_CODE_EMITTER_H
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