433 lines
17 KiB
TableGen
433 lines
17 KiB
TableGen
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//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the Hexagon target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Hexagon Subtarget features.
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//===----------------------------------------------------------------------===//
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// Hexagon Architectures
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include "HexagonDepArch.td"
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def ProcTinyCore: SubtargetFeature<"tinycore", "HexagonProcFamily",
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"TinyCore", "Hexagon Tiny Core">;
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// Hexagon ISA Extensions
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def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true",
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"Hexagon ZReg extension instructions">;
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def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
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def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
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[ExtensionHVX]>;
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def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
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[ExtensionHVX, ExtensionHVXV60]>;
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def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
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[ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62]>;
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def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
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[ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
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ExtensionZReg]>;
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def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V67", "Hexagon HVX instructions",
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[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>;
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def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
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"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
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def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
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"true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
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def ExtensionAudio: SubtargetFeature<"audio", "UseAudioOps", "true",
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"Hexagon Audio extension instructions">;
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def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true",
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"Use compound instructions">;
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def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
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"Support for instruction packets">;
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def FeaturePreV65: SubtargetFeature<"prev65", "HasPreV65", "true",
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"Support features deprecated in v65">;
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def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
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"Use constant-extended calls">;
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def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
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"Supports mem_noshuf feature">;
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def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true",
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"Use memop instructions">;
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def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
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"Support for new-value jumps", [FeaturePackets]>;
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def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true",
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"Support for new-value stores", [FeaturePackets]>;
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def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true",
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"Allow GP-relative addressing of global variables">;
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def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
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"Enable generation of duplex instruction">;
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def FeatureUnsafeFP: SubtargetFeature<"unsafe-fp", "UseUnsafeMath", "true",
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"Use unsafe FP math">;
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def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
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"true", "Reserve register R19">;
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def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim",
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"NoreturnStackElim", "true",
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"Eliminate stack allocation in a noreturn function when possible">;
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//===----------------------------------------------------------------------===//
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// Hexagon Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def UseMEMOPS : Predicate<"HST->useMemops()">;
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def UseHVX64B : Predicate<"HST->useHVX64BOps()">,
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AssemblerPredicate<(all_of ExtensionHVX64B)>;
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def UseHVX128B : Predicate<"HST->useHVX128BOps()">,
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AssemblerPredicate<(all_of ExtensionHVX128B)>;
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def UseHVX : Predicate<"HST->useHVXOps()">,
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AssemblerPredicate<(all_of ExtensionHVXV60)>;
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def UseHVXV60 : Predicate<"HST->useHVXV60Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV60)>;
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def UseHVXV62 : Predicate<"HST->useHVXV62Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV62)>;
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def UseHVXV65 : Predicate<"HST->useHVXV65Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV65)>;
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def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV66)>;
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def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">,
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AssemblerPredicate<(all_of ExtensionHVXV67)>;
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def UseAudio : Predicate<"HST->useAudioOps()">,
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AssemblerPredicate<(all_of ExtensionAudio)>;
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def UseZReg : Predicate<"HST->useZRegOps()">,
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AssemblerPredicate<(all_of ExtensionZReg)>;
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def UseCompound : Predicate<"HST->useCompound()">;
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def HasPreV65 : Predicate<"HST->hasPreV65()">,
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AssemblerPredicate<(all_of FeaturePreV65)>;
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def HasMemNoShuf : Predicate<"HST->hasMemNoShuf()">,
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AssemblerPredicate<(all_of FeatureMemNoShuf)>;
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def UseUnsafeMath : Predicate<"HST->useUnsafeMath()">;
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def NotOptTinyCore : Predicate<"!HST->isTinyCore() ||"
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"MF->getFunction().hasOptSize()"> {
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let RecomputePerFunction = 1;
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}
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def UseSmallData : Predicate<"HST->useSmallData()">;
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def Hvx64: HwMode<"+hvx-length64b">;
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def Hvx128: HwMode<"+hvx-length128b">;
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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// The classes below should remain in hierarchical order...
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class ImmRegShl;
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// ImmRegRel - Filter class used to relate instructions having reg-reg form
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// with their reg-imm counterparts.
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class ImmRegRel;
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// PredRel - Filter class used to relate non-predicated instructions with their
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// predicated forms.
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class PredRel;
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class PredNewRel: PredRel;
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// NewValueRel - Filter class used to relate regular store instructions with
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// their new-value store form.
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class NewValueRel: PredNewRel;
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class AddrModeRel: NewValueRel;
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class PostInc_BaseImm;
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class IntrinsicsRel;
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// ... through here.
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate non-predicate instructions with their
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// predicated formats - true and false.
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//
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def getPredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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// Instructions with the same BaseOpcode and isNVStore values form a row.
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let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
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// Instructions with the same predicate sense form a column.
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let ColFields = ["PredSense"];
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// The key column is the unpredicated instructions.
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let KeyCol = [""];
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// Value columns are PredSense=true and PredSense=false
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let ValueCols = [["true"], ["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-true instructions with their
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// predicate-false forms
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//
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def getFalsePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
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let ColFields = ["PredSense"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicate-false instructions with their
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// predicate-true forms
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//
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def getTruePredOpcode : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
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let ColFields = ["PredSense"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate predicated instructions with their .new
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// format.
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//
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def getPredNewOpcode : InstrMapping {
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let FilterClass = "PredNewRel";
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let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
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let ColFields = ["PNewValue"];
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let KeyCol = [""];
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let ValueCols = [["new"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate .new predicated instructions with their old
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// format.
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//
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def getPredOldOpcode : InstrMapping {
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let FilterClass = "PredNewRel";
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let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
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let ColFields = ["PNewValue"];
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let KeyCol = ["new"];
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let ValueCols = [[""]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate store instructions with their new-value
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// format.
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//
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def getNewValueOpcode : InstrMapping {
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let FilterClass = "NewValueRel";
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let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
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let ColFields = ["NValueST"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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//===----------------------------------------------------------------------===//
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// Generate mapping table to relate new-value store instructions with their old
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// format.
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//
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def getNonNVStore : InstrMapping {
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let FilterClass = "NewValueRel";
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let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
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let ColFields = ["NValueST"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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def changeAddrMode_abs_io: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
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"isFloat"];
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let ColFields = ["addrMode"];
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let KeyCol = ["Absolute"];
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let ValueCols = [["BaseImmOffset"]];
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}
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def changeAddrMode_io_abs: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
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"isFloat"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseImmOffset"];
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let ValueCols = [["Absolute"]];
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}
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def changeAddrMode_io_rr: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseImmOffset"];
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let ValueCols = [["BaseRegOffset"]];
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}
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def changeAddrMode_rr_io: InstrMapping {
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let FilterClass = "AddrModeRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseRegOffset"];
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let ValueCols = [["BaseImmOffset"]];
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}
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def changeAddrMode_pi_io: InstrMapping {
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let FilterClass = "PostInc_BaseImm";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["PostInc"];
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let ValueCols = [["BaseImmOffset"]];
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}
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def changeAddrMode_io_pi: InstrMapping {
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let FilterClass = "PostInc_BaseImm";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseImmOffset"];
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let ValueCols = [["PostInc"]];
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}
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def changeAddrMode_rr_ur: InstrMapping {
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let FilterClass = "ImmRegShl";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseRegOffset"];
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let ValueCols = [["BaseLongOffset"]];
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}
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def changeAddrMode_ur_rr : InstrMapping {
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let FilterClass = "ImmRegShl";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
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let ColFields = ["addrMode"];
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let KeyCol = ["BaseLongOffset"];
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let ValueCols = [["BaseRegOffset"]];
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}
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def getRegForm : InstrMapping {
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let FilterClass = "ImmRegRel";
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let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
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let ColFields = ["InputType"];
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let KeyCol = ["imm"];
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let ValueCols = [["reg"]];
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}
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def notTakenBranchPrediction : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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let ColFields = ["isBrTaken"];
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let KeyCol = ["true"];
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let ValueCols = [["false"]];
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}
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def takenBranchPrediction : InstrMapping {
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let FilterClass = "PredRel";
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let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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let ColFields = ["isBrTaken"];
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let KeyCol = ["false"];
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let ValueCols = [["true"]];
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}
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def getRealHWInstr : InstrMapping {
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let FilterClass = "IntrinsicsRel";
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let RowFields = ["BaseOpcode"];
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let ColFields = ["InstrType"];
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let KeyCol = ["Pseudo"];
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let ValueCols = [["Pseudo"], ["Real"]];
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}
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//===----------------------------------------------------------------------===//
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// Register File, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "HexagonSchedule.td"
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include "HexagonRegisterInfo.td"
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include "HexagonOperands.td"
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include "HexagonDepOperands.td"
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include "HexagonDepITypes.td"
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include "HexagonInstrFormats.td"
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include "HexagonDepInstrFormats.td"
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include "HexagonDepInstrInfo.td"
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include "HexagonCallingConv.td"
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include "HexagonPseudo.td"
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include "HexagonPatterns.td"
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include "HexagonPatternsHVX.td"
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include "HexagonPatternsV65.td"
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include "HexagonDepMappings.td"
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include "HexagonIntrinsics.td"
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def HexagonInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Hexagon processors supported.
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//===----------------------------------------------------------------------===//
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|
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class Proc<string Name, SchedMachineModel Model,
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list<SubtargetFeature> Features>
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: ProcessorModel<Name, Model, Features>;
|
||
|
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|
||
|
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def : Proc<"generic", HexagonModelV60,
|
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[ArchV5, ArchV55, ArchV60,
|
||
|
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FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
def : Proc<"hexagonv5", HexagonModelV5,
|
||
|
|
[ArchV5,
|
||
|
|
FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
def : Proc<"hexagonv55", HexagonModelV55,
|
||
|
|
[ArchV5, ArchV55,
|
||
|
|
FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
def : Proc<"hexagonv60", HexagonModelV60,
|
||
|
|
[ArchV5, ArchV55, ArchV60,
|
||
|
|
FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
def : Proc<"hexagonv62", HexagonModelV62,
|
||
|
|
[ArchV5, ArchV55, ArchV60, ArchV62,
|
||
|
|
FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
def : Proc<"hexagonv65", HexagonModelV65,
|
||
|
|
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
|
||
|
|
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
def : Proc<"hexagonv66", HexagonModelV66,
|
||
|
|
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,
|
||
|
|
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
def : Proc<"hexagonv67", HexagonModelV67,
|
||
|
|
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
|
||
|
|
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
|
||
|
|
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
// Need to update the correct features for tiny core.
|
||
|
|
// Disable NewValueJumps since the packetizer is unable to handle a packet with
|
||
|
|
// a new value jump and another SLOT0 instruction.
|
||
|
|
def : Proc<"hexagonv67t", HexagonModelV67T,
|
||
|
|
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
|
||
|
|
ProcTinyCore, ExtensionAudio,
|
||
|
|
FeatureCompound, FeatureMemNoShuf, FeatureMemops,
|
||
|
|
FeatureNVS, FeaturePackets, FeatureSmallData]>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Declare the target which we are implementing
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
def HexagonAsmParser : AsmParser {
|
||
|
|
let ShouldEmitMatchRegisterAltName = 1;
|
||
|
|
bit HasMnemonicFirst = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
def HexagonAsmParserVariant : AsmParserVariant {
|
||
|
|
int Variant = 0;
|
||
|
|
string TokenizingCharacters = "#()=:.<>!+*-|^&";
|
||
|
|
string BreakCharacters = "";
|
||
|
|
}
|
||
|
|
|
||
|
|
def HexagonAsmWriter : AsmWriter {
|
||
|
|
string AsmWriterClassName = "InstPrinter";
|
||
|
|
bit isMCAsmWriter = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
def Hexagon : Target {
|
||
|
|
let InstructionSet = HexagonInstrInfo;
|
||
|
|
let AssemblyParsers = [HexagonAsmParser];
|
||
|
|
let AssemblyParserVariants = [HexagonAsmParserVariant];
|
||
|
|
let AssemblyWriters = [HexagonAsmWriter];
|
||
|
|
let AllowRegisterRenaming = 1;
|
||
|
|
}
|