228 lines
6.9 KiB
C++
228 lines
6.9 KiB
C++
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//===-- VEInstPrinter.cpp - Convert VE MCInst to assembly syntax -----------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an VE MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "VEInstPrinter.h"
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#include "VE.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "ve-asmprinter"
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// The generated AsmMatcher VEGenAsmWriter uses "VE" as the target
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// namespace.
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namespace llvm {
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namespace VE {
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using namespace VE;
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}
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} // namespace llvm
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#define GET_INSTRUCTION_NAME
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#define PRINT_ALIAS_INSTR
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#include "VEGenAsmWriter.inc"
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void VEInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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// Generic registers have identical register name among register classes.
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unsigned AltIdx = VE::AsmName;
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// Misc registers have each own name, so no use alt-names.
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if (MRI.getRegClass(VE::MISCRegClassID).contains(RegNo))
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AltIdx = VE::NoRegAltName;
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OS << '%' << getRegisterName(RegNo, AltIdx);
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}
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void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &OS) {
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if (!printAliasInstr(MI, Address, STI, OS))
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printInstruction(MI, Address, STI, OS);
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printAnnotation(OS, Annot);
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}
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void VEInstPrinter::printOperand(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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if (MO.isReg()) {
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printRegName(O, MO.getReg());
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return;
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}
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if (MO.isImm()) {
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switch (MI->getOpcode()) {
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default:
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// Expects signed 32bit literals
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int32_t TruncatedImm = static_cast<int32_t>(MO.getImm());
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O << TruncatedImm;
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return;
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}
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}
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assert(MO.isExpr() && "Unknown operand kind in printOperand");
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MO.getExpr()->print(O, &MAI);
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}
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void VEInstPrinter::printMemASXOperand(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O, const char *Modifier) {
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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printOperand(MI, OpNum, STI, O);
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O << ", ";
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printOperand(MI, OpNum + 1, STI, O);
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return;
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}
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if (MI->getOperand(OpNum + 2).isImm() &&
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MI->getOperand(OpNum + 2).getImm() == 0) {
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// don't print "+0"
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} else {
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printOperand(MI, OpNum + 2, STI, O);
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}
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0 &&
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MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) {
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if (MI->getOperand(OpNum + 2).isImm() &&
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MI->getOperand(OpNum + 2).getImm() == 0) {
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O << "0";
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} else {
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// don't print "+0,+0"
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}
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} else {
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O << "(";
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0) {
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// don't print "+0"
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} else {
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printOperand(MI, OpNum + 1, STI, O);
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}
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if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) {
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// don't print "+0"
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} else {
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O << ", ";
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printOperand(MI, OpNum, STI, O);
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}
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O << ")";
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}
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}
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void VEInstPrinter::printMemASOperandASX(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O, const char *Modifier) {
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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printOperand(MI, OpNum, STI, O);
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O << ", ";
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printOperand(MI, OpNum + 1, STI, O);
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return;
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}
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0) {
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// don't print "+0"
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} else {
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printOperand(MI, OpNum + 1, STI, O);
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}
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if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) {
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0) {
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O << "0";
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} else {
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// don't print "(0)"
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}
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} else {
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O << "(, ";
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printOperand(MI, OpNum, STI, O);
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O << ")";
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}
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}
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void VEInstPrinter::printMemASOperandRRM(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O, const char *Modifier) {
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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printOperand(MI, OpNum, STI, O);
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O << ", ";
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printOperand(MI, OpNum + 1, STI, O);
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return;
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}
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0) {
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// don't print "+0"
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} else {
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printOperand(MI, OpNum + 1, STI, O);
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}
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if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) {
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0) {
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O << "0";
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} else {
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// don't print "(0)"
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}
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} else {
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O << "(";
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printOperand(MI, OpNum, STI, O);
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O << ")";
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}
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}
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void VEInstPrinter::printMemASOperandHM(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O, const char *Modifier) {
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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printOperand(MI, OpNum, STI, O);
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O << ", ";
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printOperand(MI, OpNum + 1, STI, O);
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return;
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}
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0) {
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// don't print "+0"
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} else {
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printOperand(MI, OpNum + 1, STI, O);
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}
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O << "(";
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if (MI->getOperand(OpNum).isReg())
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printOperand(MI, OpNum, STI, O);
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O << ")";
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}
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void VEInstPrinter::printMImmOperand(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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int MImm = (int)MI->getOperand(OpNum).getImm() & 0x7f;
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if (MImm > 63)
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O << "(" << MImm - 64 << ")0";
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else
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O << "(" << MImm << ")1";
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}
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void VEInstPrinter::printCCOperand(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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int CC = (int)MI->getOperand(OpNum).getImm();
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O << VECondCodeToString((VECC::CondCode)CC);
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}
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void VEInstPrinter::printRDOperand(const MCInst *MI, int OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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int RD = (int)MI->getOperand(OpNum).getImm();
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O << VERDToString((VERD::RoundingMode)RD);
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}
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