200 lines
9.6 KiB
LLVM
200 lines
9.6 KiB
LLVM
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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;
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; CLS
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;
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define <vscale x 16 x i8> @cls_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: cls_i8:
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; CHECK: cls z0.b, p0/m, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8> %a,
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<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @cls_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: cls_i16:
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; CHECK: cls z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @cls_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: cls_i32:
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; CHECK: cls z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @cls_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: cls_i64:
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; CHECK: cls z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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;
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; CLZ
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;
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define <vscale x 16 x i8> @clz_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: clz_i8:
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; CHECK: clz z0.b, p0/m, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> %a,
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<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @clz_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: clz_i16:
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; CHECK: clz z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @clz_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: clz_i32:
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; CHECK: clz z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @clz_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: clz_i64:
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; CHECK: clz z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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;
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; CNT
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;
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define <vscale x 16 x i8> @cnt_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: cnt_i8:
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; CHECK: cnt z0.b, p0/m, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8> %a,
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<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @cnt_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: cnt_i16:
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; CHECK: cnt z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @cnt_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: cnt_i32:
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; CHECK: cnt z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @cnt_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: cnt_i64:
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; CHECK: cnt z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x i16> @cnt_f16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b) {
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; CHECK-LABEL: cnt_f16:
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; CHECK: cnt z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16> %a,
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<vscale x 8 x i1> %pg,
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<vscale x 8 x half> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 8 x i16> @cnt_bf16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %b) #0 {
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; CHECK-LABEL: cnt_bf16:
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; CHECK: cnt z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> %a,
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<vscale x 8 x i1> %pg,
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<vscale x 8 x bfloat> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @cnt_f32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
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; CHECK-LABEL: cnt_f32:
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; CHECK: cnt z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32> %a,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x float> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @cnt_f64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
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; CHECK-LABEL: cnt_f64:
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; CHECK: cnt z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64> %a,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x double> %b)
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ret <vscale x 2 x i64> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.cls.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.cls.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.cls.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.cnt.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x bfloat>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.cnt.nxv2f64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x double>)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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