109 lines
5.6 KiB
LLVM
109 lines
5.6 KiB
LLVM
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI,SICI,SICIVI,GCN %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SICI,CIVI,SICIVI,GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,SICIVI,GFX89,GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX89,GCN %s
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; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset:
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; GFX9-NOT: m0
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; SICIVI-DAG: s_mov_b32 m0
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; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
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; SICI-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
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; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c
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; GFX89-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70
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; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
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; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
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; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
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; GCN: s_endpgm
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define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, [8 x i32], i32 addrspace(3)* %ptr, [8 x i32], i32 %swap) nounwind {
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%gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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%pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
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%result = extractvalue { i32, i1 } %pair, 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset:
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; GFX9-NOT: m0
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; SICIVI-DAG: s_mov_b32 m0
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; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SICI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
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; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
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; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
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; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
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; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
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; GCN: [[RESULT]]
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; GCN: s_endpgm
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define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind {
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%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
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%pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
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%result = extractvalue { i64, i1 } %pair, 0
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store i64 %result, i64 addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_bad_si_offset
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; GFX9-NOT: m0
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; SI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CIVI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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; GFX9: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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; GCN: s_endpgm
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define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap, i32 %a, i32 %b) nounwind {
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%sub = sub i32 %a, %b
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%add = add i32 %sub, 4
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%gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
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%pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
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%result = extractvalue { i32, i1 } %pair, 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_cmpxchg_noret_i32_offset:
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; GFX9-NOT: m0
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; SICIVI-DAG: s_mov_b32 m0
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; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
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; SICI-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x12
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; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
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; GFX89-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x48
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; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
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; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
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; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
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; GCN: s_endpgm
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define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, [8 x i32], i32 %swap) nounwind {
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%gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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%pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
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%result = extractvalue { i32, i1 } %pair, 0
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset:
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; GFX9-NOT: m0
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; SICIVI-DAG: s_mov_b32 m0
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; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
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; SICI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
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; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
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; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
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; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
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; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
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; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
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; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
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; GCN: s_endpgm
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define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind {
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%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
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%pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
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%result = extractvalue { i64, i1 } %pair, 0
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ret void
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}
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