50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)
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; GCN-LABEL: {{^}}frexp_exp_f16
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
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; GCN: buffer_store_short v[[R_I16]]
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define amdgpu_kernel void @frexp_exp_f16(
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i16 addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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store i16 %r.val, i16 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}frexp_exp_f16_sext
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
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; VI: v_bfe_i32 v[[R_I32:[0-9]+]], v[[R_I16]], 0, 16{{$}}
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; GCN: buffer_store_dword v[[R_I32]]
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define amdgpu_kernel void @frexp_exp_f16_sext(
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i32 addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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%r.val.sext = sext i16 %r.val to i32
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store i32 %r.val.sext, i32 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}frexp_exp_f16_zext
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
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; VI: v_and_b32_e32 v[[R_I32:[0-9]+]], 0xffff, v[[R_I16]]
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; GCN: buffer_store_dword v[[R_I32]]
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define amdgpu_kernel void @frexp_exp_f16_zext(
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i32 addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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%r.val.zext = zext i16 %r.val to i32
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store i32 %r.val.zext, i32 addrspace(1)* %r
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ret void
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}
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