913 lines
48 KiB
LLVM
913 lines
48 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s
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define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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; GFX9-LABEL: load_1d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_1d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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; GFX9-LABEL: load_2d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 ; encoding: [0x08,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%t = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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; GFX9-LABEL: load_3d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_3d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; encoding: [0x10,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%r = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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; GFX9-LABEL: load_cube:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_cube:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16 ; encoding: [0x18,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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; GFX9-LABEL: load_1darray:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_1darray:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 ; encoding: [0x20,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%slice = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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; GFX9-LABEL: load_2darray:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_2darray:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 ; encoding: [0x28,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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; GFX9-LABEL: load_2dmsaa:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_2dmsaa:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x30,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%fragid = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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; GFX9-LABEL: load_2darraymsaa:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x00,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_2darraymsaa:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x38,0x1f,0x00,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%fragid = extractelement <2 x i16> %coords_hi, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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; GFX9-LABEL: load_mip_1d:
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; GFX9: ; %bb.0: ; %main_body
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; GFX9-NEXT: image_load_mip v[0:3], v0, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x04,0xf0,0x00,0x00,0x00,0x00]
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: load_mip_1d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load_mip v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x1f,0x04,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%mip = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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; GFX9-LABEL: load_mip_2d:
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||
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; GFX9: ; %bb.0: ; %main_body
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||
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; GFX9-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x04,0xf0,0x00,0x00,0x00,0x00]
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||
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; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
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; GFX9-NEXT: ; return to shader part epilog
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||
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;
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; GFX10-LABEL: load_mip_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 ; encoding: [0x08,0x1f,0x04,0xf0,0x00,0x00,0x00,0x40]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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||
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%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%mip = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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||
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ret <4 x float> %v
|
||
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}
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||
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||
|
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define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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||
|
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; GFX9-LABEL: load_mip_3d:
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||
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; GFX9: ; %bb.0: ; %main_body
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||
|
|
; GFX9-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x04,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_mip_3d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; encoding: [0x10,0x1f,0x04,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%r = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: load_mip_cube:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x04,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_mip_cube:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16 ; encoding: [0x18,0x1f,0x04,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: load_mip_1darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x04,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_mip_1darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 ; encoding: [0x20,0x1f,0x04,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%slice = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: load_mip_2darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x04,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_mip_2darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 ; encoding: [0x28,0x1f,0x04,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_1d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_1d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_2d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_2d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 ; encoding: [0x08,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords, i32 1
|
||
|
|
call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_3d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_3d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; encoding: [0x10,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%r = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_cube:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_cube:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16 ; encoding: [0x18,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_1darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_1darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 ; encoding: [0x20,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%slice = extractelement <2 x i16> %coords, i32 1
|
||
|
|
call void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_2darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_2darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 ; encoding: [0x28,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_2dmsaa:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_2dmsaa:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x30,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%fragid = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_2darraymsaa:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_2darraymsaa:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x38,0x1f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%fragid = extractelement <2 x i16> %coords_hi, i32 1
|
||
|
|
call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_mip_1d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store_mip v[0:3], v4, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x24,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_mip_1d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store_mip v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x1f,0x24,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 1
|
||
|
|
call void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_mip_2d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x24,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_mip_2d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 ; encoding: [0x08,0x1f,0x24,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_mip_3d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x24,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_mip_3d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; encoding: [0x10,0x1f,0x24,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%r = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||
|
|
call void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_mip_cube:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x24,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_mip_cube:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16 ; encoding: [0x18,0x1f,0x24,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||
|
|
call void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_mip_1darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x24,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_mip_1darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 ; encoding: [0x20,0x1f,0x24,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%slice = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||
|
|
; GFX9-LABEL: store_mip_2darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x24,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_mip_2darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 ; encoding: [0x28,0x1f,0x24,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||
|
|
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||
|
|
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||
|
|
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||
|
|
call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_1d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_1d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_2d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_2d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 ; encoding: [0x08,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_3d:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_3d:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; encoding: [0x10,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_cube:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_cube:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16 ; encoding: [0x18,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_1darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_1darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 ; encoding: [0x20,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_2darray:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_2darray:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 ; encoding: [0x28,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_2dmsaa:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_2dmsaa:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x30,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: getresinfo_2darraymsaa:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da ; encoding: [0x00,0xdf,0x38,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_2darraymsaa:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x38,0x1f,0x38,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: load_1d_V1:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load v0, v0, s[0:7] dmask:0x8 unorm a16 ; encoding: [0x00,0x98,0x00,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_1d_V1:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x18,0x00,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call float @llvm.amdgcn.image.load.1d.f32.i16(i32 8, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret float %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: load_1d_V2:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm a16 ; encoding: [0x00,0x99,0x00,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_1d_V2:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x19,0x00,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 9, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <2 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_1d_V1:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v0, v1, s[0:7] dmask:0x2 unorm a16 ; encoding: [0x00,0x92,0x20,0xf0,0x01,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_1d_V1:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x12,0x20,0xf0,0x01,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_1d_V2:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc unorm a16 ; encoding: [0x00,0x9c,0x20,0xf0,0x02,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_1d_V2:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x1c,0x20,0xf0,0x02,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: load_1d_glc:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc a16 ; encoding: [0x00,0xbf,0x00,0xf0,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_1d_glc:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc a16 ; encoding: [0x00,0x3f,0x00,0xf0,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: load_1d_slc:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc a16 ; encoding: [0x00,0x9f,0x00,0xf2,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_1d_slc:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm slc a16 ; encoding: [0x00,0x1f,0x00,0xf2,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: load_1d_glc_slc:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc a16 ; encoding: [0x00,0xbf,0x00,0xf2,0x00,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: load_1d_glc_slc:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc slc a16 ; encoding: [0x00,0x3f,0x00,0xf2,0x00,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
|
||
|
|
ret <4 x float> %v
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_1d_glc:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc a16 ; encoding: [0x00,0xbf,0x20,0xf0,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_1d_glc:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc a16 ; encoding: [0x00,0x3f,0x20,0xf0,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_1d_slc:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc a16 ; encoding: [0x00,0x9f,0x20,0xf2,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_1d_slc:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm slc a16 ; encoding: [0x00,0x1f,0x20,0xf2,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||
|
|
; GFX9-LABEL: store_1d_glc_slc:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc a16 ; encoding: [0x00,0xbf,0x20,0xf2,0x04,0x00,0x00,0x00]
|
||
|
|
; GFX9-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: store_1d_glc_slc:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc slc a16 ; encoding: [0x00,0x3f,0x20,0xf2,0x04,0x00,0x00,0x40]
|
||
|
|
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
|
||
|
|
main_body:
|
||
|
|
%s = extractelement <2 x i16> %coords, i32 0
|
||
|
|
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) #0 {
|
||
|
|
; GFX9-LABEL: getresinfo_dmask0:
|
||
|
|
; GFX9: ; %bb.0: ; %main_body
|
||
|
|
; GFX9-NEXT: ; return to shader part epilog
|
||
|
|
;
|
||
|
|
; GFX10-LABEL: getresinfo_dmask0:
|
||
|
|
; GFX10: ; %bb.0: ; %main_body
|
||
|
|
; GFX10-NEXT: ; return to shader part epilog
|
||
|
|
main_body:
|
||
|
|
%mip = extractelement <2 x i16> %coords, i32 0
|
||
|
|
%r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 0, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||
|
|
ret <4 x float> %r
|
||
|
|
}
|
||
|
|
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
|
||
|
|
declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
|
||
|
|
declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||
|
|
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
declare <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||
|
|
|
||
|
|
declare float @llvm.amdgcn.image.load.1d.f32.i16(i32, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare float @llvm.amdgcn.image.load.2d.f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32, i16, <8 x i32>, i32, i32) #1
|
||
|
|
declare void @llvm.amdgcn.image.store.1d.f32.i16(float, i32, i16, <8 x i32>, i32, i32) #0
|
||
|
|
declare void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float>, i32, i16, <8 x i32>, i32, i32) #0
|
||
|
|
|
||
|
|
attributes #0 = { nounwind }
|
||
|
|
attributes #1 = { nounwind readonly }
|
||
|
|
attributes #2 = { nounwind readnone }
|