85 lines
3.3 KiB
LLVM
85 lines
3.3 KiB
LLVM
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
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declare i32 @llvm.amdgcn.readlane(i32, i32) #0
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; CHECK-LABEL: {{^}}test_readlane_sreg_sreg:
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; CHECK-NOT: v_readlane_b32
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define amdgpu_kernel void @test_readlane_sreg_sreg(i32 %src0, i32 %src1) #1 {
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%readlane = call i32 @llvm.amdgcn.readlane(i32 %src0, i32 %src1)
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call void asm sideeffect "; use $0", "s"(i32 %readlane)
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ret void
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}
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; CHECK-LABEL: {{^}}test_readlane_vreg_sreg:
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; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @test_readlane_vreg_sreg(i32 %src0, i32 %src1) #1 {
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%vgpr = call i32 asm sideeffect "; def $0", "=v"()
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%readlane = call i32 @llvm.amdgcn.readlane(i32 %vgpr, i32 %src1)
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call void asm sideeffect "; use $0", "s"(i32 %readlane)
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ret void
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}
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; CHECK-LABEL: {{^}}test_readlane_imm_sreg:
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; CHECK-NOT: v_readlane_b32
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define amdgpu_kernel void @test_readlane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
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%readlane = call i32 @llvm.amdgcn.readlane(i32 32, i32 %src1)
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store i32 %readlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_readlane_vregs:
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; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
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; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, [[LANE]]
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define amdgpu_kernel void @test_readlane_vregs(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid
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%args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
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%value = extractelement <2 x i32> %args, i32 0
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%lane = extractelement <2 x i32> %args, i32 1
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%readlane = call i32 @llvm.amdgcn.readlane(i32 %value, i32 %lane)
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store i32 %readlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; TODO: m0 should be folded.
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; CHECK-LABEL: {{^}}test_readlane_m0_sreg:
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; CHECK: s_mov_b32 m0, -1
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; CHECK: v_mov_b32_e32 [[VVAL:v[0-9]]], m0
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VVAL]]
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define amdgpu_kernel void @test_readlane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
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%m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"()
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%readlane = call i32 @llvm.amdgcn.readlane(i32 %m0, i32 %src1)
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store i32 %readlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_readlane_vgpr_imm:
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; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 32
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define amdgpu_kernel void @test_readlane_vgpr_imm(i32 addrspace(1)* %out) #1 {
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%vgpr = call i32 asm sideeffect "; def $0", "=v"()
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%readlane = call i32 @llvm.amdgcn.readlane(i32 %vgpr, i32 32) #0
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store i32 %readlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_readlane_copy_from_sgpr:
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; CHECK: ;;#ASMSTART
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; CHECK-NEXT: s_mov_b32 [[SGPR:s[0-9]+]]
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; CHECK: ;;#ASMEND
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; CHECK-NOT: [[SGPR]]
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; CHECK-NOT: readlane
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; CHECK: v_mov_b32_e32 [[VCOPY:v[0-9]+]], [[SGPR]]
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VCOPY]]
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define amdgpu_kernel void @test_readlane_copy_from_sgpr(i32 addrspace(1)* %out) #1 {
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%sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()
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%readfirstlane = call i32 @llvm.amdgcn.readlane(i32 %sgpr, i32 7)
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store i32 %readfirstlane, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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attributes #0 = { nounwind readnone convergent }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readnone }
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