71 lines
2.2 KiB
LLVM
71 lines
2.2 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner -enable-pipeliner-opt-size \
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; RUN: -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 \
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; RUN: -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \
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; RUN: < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Disable expand-condsets because it will assert on undefined registers.
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; Test that we change the CFG correctly for pipelined loops where the trip
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; count is a compile-time constant, and the trip count is the same as the
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; number of prolog blocks (i.e., stages).
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; CHECK: memb(r{{[0-9]+}}+#0) =
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; CHECK: memb(r{{[0-9]+}}+#0) =
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; Function Attrs: nounwind optsize
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define void @f0(i1 %x) #0 {
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b0:
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br label %b1
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b1: ; preds = %b5, %b0
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%v0 = load i16, i16* undef, align 2, !tbaa !0
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%v1 = sext i16 %v0 to i32
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%v2 = load i16, i16* undef, align 2, !tbaa !0
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%v3 = sext i16 %v2 to i32
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%v4 = and i32 %v1, 7
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%v5 = and i32 %v3, 7
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br label %b2
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b2: ; preds = %b4, %b1
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br label %b3
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b3: ; preds = %b3, %b2
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%v6 = phi i32 [ 0, %b2 ], [ %v22, %b3 ]
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%v7 = add i32 %v6, undef
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%v8 = icmp slt i32 undef, %v7
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%v9 = add nsw i32 %v7, 1
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%v10 = select i1 %x, i32 1, i32 %v9
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%v11 = add i32 %v10, 0
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%v12 = getelementptr inbounds i8, i8* null, i32 %v11
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%v13 = load i8, i8* %v12, align 1, !tbaa !4
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%v14 = zext i8 %v13 to i32
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%v15 = mul i32 %v14, %v4
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%v16 = add i32 %v15, 0
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%v17 = mul i32 %v16, %v5
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%v18 = add i32 %v17, 32
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%v19 = add i32 %v18, 0
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%v20 = lshr i32 %v19, 6
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%v21 = trunc i32 %v20 to i8
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store i8 %v21, i8* undef, align 1, !tbaa !4
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%v22 = add i32 %v6, 1
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%v23 = icmp eq i32 %v22, 2
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br i1 %v23, label %b4, label %b3
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b4: ; preds = %b3
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br i1 undef, label %b5, label %b2
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b5: ; preds = %b4
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br i1 undef, label %b1, label %b6
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b6: ; preds = %b5
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ret void
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}
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attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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!4 = !{!2, !2, i64 0}
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