39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Test that we generate the correct value for a Phi in the epilog
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; that is for a value defined two stages earlier. An extra copy in the
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; epilog means the schedule is incorrect.
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; CHECK: endloop0
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; CHECK-NOT: r{{[0-9]+}} = r{{[0-9]+}}
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; Function Attrs: nounwind
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define void @f0(i32 %a0, i32* %a1, [1000 x i32]* %a2, i32* %a3, i32* %a4) #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ %v8, %b1 ], [ 1, %b0 ]
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%v1 = load i32, i32* %a3, align 4, !tbaa !0
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%v2 = getelementptr inbounds i32, i32* %a1, i32 %v0
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%v3 = load i32, i32* %v2, align 4, !tbaa !0
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%v4 = load i32, i32* %a4, align 4, !tbaa !0
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%v5 = mul nsw i32 %v4, %v3
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%v6 = add nsw i32 %v5, %v1
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%v7 = getelementptr inbounds [1000 x i32], [1000 x i32]* %a2, i32 %v0, i32 0
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store i32 %v6, i32* %v7, align 4, !tbaa !0
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%v8 = add nsw i32 %v0, 1
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%v9 = icmp eq i32 %v8, %a0
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br i1 %v9, label %b2, label %b1
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b2: ; preds = %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"long", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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