58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Check that we correctly rename instructions that use a Phi's loop value,
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; and the Phi and loop value are defined after the instruction.
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%s.0 = type { [4 x i8], i16, i16, i32, [8 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x %s.1], [4 x i8], i32, i32, [4 x i8], [14 x %s.2] }
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%s.1 = type { i32, i32 }
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%s.2 = type { [4 x i8] }
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; Function Attrs: nounwind
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define void @f0(%s.0* nocapture %a0) #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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unreachable
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b2: ; preds = %b0
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br label %b8
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b3: ; preds = %b9
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unreachable
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b4: ; preds = %b9
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br i1 undef, label %b7, label %b5
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b5: ; preds = %b4
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br i1 undef, label %b6, label %b7
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b6: ; preds = %b6, %b5
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%v0 = phi i32 [ %v10, %b6 ], [ 0, %b5 ]
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%v1 = load i32, i32* undef, align 4
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%v2 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 29, i32 %v0
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%v3 = bitcast %s.2* %v2 to i32*
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%v4 = load i32, i32* %v3, align 4
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%v5 = and i32 %v1, 65535
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%v6 = and i32 %v4, -65536
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%v7 = or i32 %v6, %v5
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%v8 = and i32 %v7, -2031617
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%v9 = or i32 %v8, 0
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store i32 %v9, i32* %v3, align 4
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%v10 = add nsw i32 %v0, 1
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%v11 = icmp eq i32 %v10, undef
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br i1 %v11, label %b7, label %b6
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b7: ; preds = %b6, %b5, %b4
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ret void
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b8: ; preds = %b8, %b2
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br i1 undef, label %b9, label %b8
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b9: ; preds = %b8
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br i1 undef, label %b3, label %b4
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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