87 lines
3.0 KiB
LLVM
87 lines
3.0 KiB
LLVM
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; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Test that we order instruction within a packet correctly. In this case,
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; we added a definition of a value after the use in a packet, which
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; caused an assert.
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define void @f0(i32 %a0) {
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b0:
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%v0 = ashr i32 %a0, 1
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br i1 undef, label %b3, label %b1
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b1: ; preds = %b1, %b0
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%v1 = phi i32 [ %v23, %b1 ], [ undef, %b0 ]
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%v2 = phi i64 [ %v14, %b1 ], [ 0, %b0 ]
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%v3 = phi i64 [ %v11, %b1 ], [ 0, %b0 ]
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%v4 = phi i32 [ %v25, %b1 ], [ 0, %b0 ]
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%v5 = phi i32 [ %v6, %b1 ], [ undef, %b0 ]
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%v6 = phi i32 [ %v20, %b1 ], [ undef, %b0 ]
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%v7 = phi i32 [ %v24, %b1 ], [ undef, %b0 ]
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%v8 = tail call i32 @llvm.hexagon.A2.combine.lh(i32 %v6, i32 %v5)
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%v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 undef)
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%v10 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v1, i32 undef)
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%v11 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v3, i64 %v9, i64 undef)
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%v12 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5)
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%v13 = tail call i64 @llvm.hexagon.S2.valignib(i64 %v10, i64 undef, i32 2)
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%v14 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v12, i64 %v13)
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%v15 = inttoptr i32 %v7 to i16*
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%v16 = load i16, i16* %v15, align 2
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%v17 = sext i16 %v16 to i32
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%v18 = add nsw i32 %v7, -8
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%v19 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v12, i64 0)
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%v20 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 %v17, i32 %v1)
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%v21 = inttoptr i32 %v18 to i16*
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%v22 = load i16, i16* %v21, align 2
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%v23 = sext i16 %v22 to i32
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%v24 = add nsw i32 %v7, -16
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%v25 = add nsw i32 %v4, 1
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%v26 = icmp eq i32 %v25, %v0
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br i1 %v26, label %b2, label %b1
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b2: ; preds = %b1
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%v27 = phi i64 [ %v19, %b1 ]
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%v28 = phi i64 [ %v14, %b1 ]
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%v29 = phi i64 [ %v11, %b1 ]
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%v30 = trunc i64 %v27 to i32
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%v31 = trunc i64 %v28 to i32
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%v32 = lshr i64 %v29, 32
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%v33 = trunc i64 %v32 to i32
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br label %b3
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b3: ; preds = %b2, %b0
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%v34 = phi i32 [ %v30, %b2 ], [ undef, %b0 ]
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%v35 = phi i32 [ %v31, %b2 ], [ undef, %b0 ]
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%v36 = phi i32 [ %v33, %b2 ], [ undef, %b0 ]
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%v37 = bitcast i8* undef to i32*
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store i32 %v35, i32* %v37, align 4
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%v38 = getelementptr inbounds i8, i8* null, i32 8
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%v39 = bitcast i8* %v38 to i32*
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store i32 %v34, i32* %v39, align 4
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%v40 = bitcast i8* undef to i32*
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store i32 %v36, i32* %v40, align 4
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call void @llvm.trap()
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.combine.lh(i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.valignib(i64, i64, i32) #0
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; Function Attrs: noreturn nounwind
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declare void @llvm.trap() #1
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attributes #0 = { nounwind readnone }
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attributes #1 = { noreturn nounwind }
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