38 lines
1.2 KiB
LLVM
38 lines
1.2 KiB
LLVM
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; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Test that the instruction ordering code in the pipeliner fixes up dependences
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; between post-increment register definitions and uses so that the register
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; allocator does not allocate an additional register. The following test case
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; should generate a single packet.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: {
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; CHECK-NOT: {
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; CHECK: :endloop0
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define void @test(i64* nocapture %v1, i64 %v2, i32 %len) local_unnamed_addr #0 {
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entry:
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%cmp7 = icmp sgt i32 %len, 0
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br i1 %cmp7, label %for.body, label %for.end
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for.body:
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%arrayidx.phi = phi i64* [ %arrayidx.inc, %for.body ], [ %v1, %entry ]
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%i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%0 = load i64, i64* %arrayidx.phi, align 8
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%1 = tail call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %0, i64 %v2)
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store i64 %1, i64* %arrayidx.phi, align 8
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%inc = add nuw nsw i32 %i.08, 1
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%exitcond = icmp eq i32 %inc, %len
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%arrayidx.inc = getelementptr i64, i64* %arrayidx.phi, i32 1
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret void
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}
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declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readnone }
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