49 lines
1.5 KiB
LLVM
49 lines
1.5 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Make sure pipeliner handle physical registers (e.g., used in
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; inline asm
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@g0 = external global i32*, align 4
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; Function Attrs: nounwind
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define i32 @f0(i32 %a0, i8** nocapture %a1) #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b0
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unreachable
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b2: ; preds = %b0
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br label %b3
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b3: ; preds = %b3, %b2
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br i1 undef, label %b4, label %b3
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b4: ; preds = %b3
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br label %b5
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b5: ; preds = %b5, %b4
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%v0 = phi i32* [ inttoptr (i32 33554432 to i32*), %b4 ], [ %v4, %b5 ]
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%v1 = phi i32 [ 0, %b4 ], [ %v5, %b5 ]
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%v2 = ptrtoint i32* %v0 to i32
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tail call void asm sideeffect " r1 = $1\0A r0 = $0\0A memw(r0) = r1\0A dcfetch(r0)\0A", "r,r,~{r0},~{r1}"(i32 %v2, i32 %v1) #0
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%v3 = load i32*, i32** @g0, align 4
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%v4 = getelementptr inbounds i32, i32* %v3, i32 1
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store i32* %v4, i32** @g0, align 4
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%v5 = add nsw i32 %v1, 1
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%v6 = icmp eq i32 %v5, 200
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br i1 %v6, label %b6, label %b5
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b6: ; preds = %b5
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br label %b7
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b7: ; preds = %b7, %b6
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br i1 undef, label %b8, label %b7
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b8: ; preds = %b7
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ret i32 0
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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