179 lines
6.4 KiB
LLVM
179 lines
6.4 KiB
LLVM
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; RUN: llc -march=hexagon -O0 < %s | FileCheck --check-prefix=CHECKO0 %s
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; KP: Removed -O2 check. The code has become more aggressively optimized
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; (some loads were found to be redundant and have been removed completely),
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; and verifying correct code generation has become more difficult than
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; its worth.
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; CHECK: v{{[0-9]*}} = vsplat(r{{[0-9]*}})
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; CHECK: v{{[0-9]*}} = vsplat(r{{[0-9]*}})
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; CHECKO0: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}
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; CHECKO0: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)
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; CHECKO0: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)
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; Allow .cur loads.
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; CHECKO2: v{{[0-9].*}} = vmem(r{{[0-9]*}}+#0)
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; CHECKO2: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}
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; CHECKO2: v{{[0-9].*}} = vmem(r{{[0-9]*}}+#0)
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; CHECK: v{{[0-9]*}}:{{[0-9]*}} = vcombine(v{{[0-9]*}},v{{[0-9]*}})
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; CHECK: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}
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; CHECK: vmem(r{{[0-9]*}}+#32) = v{{[0-9]*}}
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; CHECK: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)
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; CHECK: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#32)
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; CHECK: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}
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; CHECK: vmem(r{{[0-9]*}}+#32) = v{{[0-9]*}}
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target triple = "hexagon"
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@g0 = common global [10 x <32 x i32>] zeroinitializer, align 64
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@g1 = private unnamed_addr constant [11 x i8] c"c[%d]= %x\0A\00", align 8
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@g2 = common global [10 x <16 x i32>] zeroinitializer, align 64
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@g3 = common global [10 x <16 x i32>] zeroinitializer, align 64
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@g4 = common global [10 x <32 x i32>] zeroinitializer, align 64
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declare i32 @f0(i8*, ...)
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; Function Attrs: nounwind
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define void @f1(i32 %a0) #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca i32*, align 4
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%v2 = alloca i32, align 4
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store i32 %a0, i32* %v0, align 4
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store i32* getelementptr inbounds ([10 x <32 x i32>], [10 x <32 x i32>]* @g0, i32 0, i32 0, i32 0), i32** %v1, align 4
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%v3 = load i32, i32* %v0, align 4
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%v4 = load i32*, i32** %v1, align 4
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%v5 = getelementptr inbounds i32, i32* %v4, i32 %v3
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store i32* %v5, i32** %v1, align 4
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store i32 0, i32* %v2, align 4
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br label %b1
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b1: ; preds = %b3, %b0
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%v6 = load i32, i32* %v2, align 4
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%v7 = icmp slt i32 %v6, 16
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br i1 %v7, label %b2, label %b4
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b2: ; preds = %b1
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%v8 = load i32, i32* %v2, align 4
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%v9 = load i32*, i32** %v1, align 4
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%v10 = getelementptr inbounds i32, i32* %v9, i32 1
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store i32* %v10, i32** %v1, align 4
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%v11 = load i32, i32* %v9, align 4
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%v12 = call i32 (i8*, ...) @f0(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @g1, i32 0, i32 0), i32 %v8, i32 %v11)
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br label %b3
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b3: ; preds = %b2
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%v13 = load i32, i32* %v2, align 4
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%v14 = add nsw i32 %v13, 1
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store i32 %v14, i32* %v2, align 4
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br label %b1
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b4: ; preds = %b1
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ret void
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}
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; Function Attrs: nounwind
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define i32 @f2() #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca i32, align 4
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store i32 0, i32* %v0
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store i32 0, i32* %v1, align 4
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br label %b1
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b1: ; preds = %b3, %b0
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%v2 = load i32, i32* %v1, align 4
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%v3 = icmp slt i32 %v2, 3
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br i1 %v3, label %b2, label %b4
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b2: ; preds = %b1
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%v4 = load i32, i32* %v1, align 4
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%v5 = add nsw i32 %v4, 1
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%v6 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v5)
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%v7 = load i32, i32* %v1, align 4
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%v8 = getelementptr inbounds [10 x <16 x i32>], [10 x <16 x i32>]* @g2, i32 0, i32 %v7
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store <16 x i32> %v6, <16 x i32>* %v8, align 64
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%v9 = load i32, i32* %v1, align 4
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%v10 = mul nsw i32 %v9, 10
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%v11 = add nsw i32 %v10, 1
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%v12 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v11)
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%v13 = load i32, i32* %v1, align 4
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%v14 = getelementptr inbounds [10 x <16 x i32>], [10 x <16 x i32>]* @g3, i32 0, i32 %v13
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store <16 x i32> %v12, <16 x i32>* %v14, align 64
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%v15 = load i32, i32* %v1, align 4
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%v16 = getelementptr inbounds [10 x <16 x i32>], [10 x <16 x i32>]* @g2, i32 0, i32 %v15
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%v17 = load <16 x i32>, <16 x i32>* %v16, align 64
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%v18 = load i32, i32* %v1, align 4
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%v19 = getelementptr inbounds [10 x <16 x i32>], [10 x <16 x i32>]* @g3, i32 0, i32 %v18
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%v20 = load <16 x i32>, <16 x i32>* %v19, align 64
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%v21 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v17, <16 x i32> %v20)
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%v22 = load i32, i32* %v1, align 4
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%v23 = getelementptr inbounds [10 x <32 x i32>], [10 x <32 x i32>]* @g4, i32 0, i32 %v22
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store <32 x i32> %v21, <32 x i32>* %v23, align 64
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br label %b3
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b3: ; preds = %b2
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%v24 = load i32, i32* %v1, align 4
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%v25 = add nsw i32 %v24, 1
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store i32 %v25, i32* %v1, align 4
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br label %b1
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b4: ; preds = %b1
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store i32 0, i32* %v1, align 4
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br label %b5
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b5: ; preds = %b7, %b4
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%v26 = load i32, i32* %v1, align 4
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%v27 = icmp slt i32 %v26, 3
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br i1 %v27, label %b6, label %b8
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b6: ; preds = %b5
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%v28 = load i32, i32* %v1, align 4
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%v29 = getelementptr inbounds [10 x <32 x i32>], [10 x <32 x i32>]* @g4, i32 0, i32 %v28
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%v30 = load <32 x i32>, <32 x i32>* %v29, align 64
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%v31 = load i32, i32* %v1, align 4
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%v32 = getelementptr inbounds [10 x <32 x i32>], [10 x <32 x i32>]* @g0, i32 0, i32 %v31
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store <32 x i32> %v30, <32 x i32>* %v32, align 64
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br label %b7
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b7: ; preds = %b6
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%v33 = load i32, i32* %v1, align 4
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%v34 = add nsw i32 %v33, 1
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store i32 %v34, i32* %v1, align 4
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br label %b5
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b8: ; preds = %b5
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store i32 0, i32* %v1, align 4
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br label %b9
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b9: ; preds = %b11, %b8
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%v35 = load i32, i32* %v1, align 4
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%v36 = icmp slt i32 %v35, 3
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br i1 %v36, label %b10, label %b12
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b10: ; preds = %b9
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%v37 = load i32, i32* %v1, align 4
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%v38 = mul nsw i32 %v37, 16
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call void @f1(i32 %v38)
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br label %b11
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b11: ; preds = %b10
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%v39 = load i32, i32* %v1, align 4
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%v40 = add nsw i32 %v39, 1
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store i32 %v40, i32* %v1, align 4
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br label %b9
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b12: ; preds = %b9
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ret i32 0
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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