36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
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define zeroext i1 @half_is_nan(half %a) nounwind {
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; RV32IZFH-LABEL: half_is_nan:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa0
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: half_is_nan:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa0
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: ret
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%1 = fcmp uno half %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @half_not_nan(half %a) nounwind {
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; RV32IZFH-LABEL: half_not_nan:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: half_not_nan:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa0
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; RV64IZFH-NEXT: ret
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%1 = fcmp ord half %a, 0.000000e+00
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ret i1 %1
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}
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