131 lines
4.8 KiB
LLVM
131 lines
4.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32
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define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
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; RISCV32-LABEL: muloti_test:
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; RISCV32: # %bb.0: # %start
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; RISCV32-NEXT: addi sp, sp, -96
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; RISCV32-NEXT: sw ra, 92(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s0, 88(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s1, 84(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s2, 80(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s3, 76(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s4, 72(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s5, 68(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s6, 64(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s7, 60(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: sw s8, 56(sp) # 4-byte Folded Spill
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; RISCV32-NEXT: lw s2, 12(a1)
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; RISCV32-NEXT: lw s6, 8(a1)
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; RISCV32-NEXT: lw s3, 12(a2)
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; RISCV32-NEXT: lw s7, 8(a2)
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; RISCV32-NEXT: lw s0, 0(a1)
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; RISCV32-NEXT: lw s8, 4(a1)
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; RISCV32-NEXT: lw s1, 0(a2)
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; RISCV32-NEXT: lw s5, 4(a2)
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; RISCV32-NEXT: mv s4, a0
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; RISCV32-NEXT: sw zero, 20(sp)
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; RISCV32-NEXT: sw zero, 16(sp)
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; RISCV32-NEXT: sw zero, 36(sp)
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; RISCV32-NEXT: sw zero, 32(sp)
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; RISCV32-NEXT: sw s5, 12(sp)
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; RISCV32-NEXT: sw s1, 8(sp)
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; RISCV32-NEXT: sw s8, 28(sp)
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; RISCV32-NEXT: addi a0, sp, 40
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; RISCV32-NEXT: addi a1, sp, 24
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; RISCV32-NEXT: addi a2, sp, 8
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; RISCV32-NEXT: sw s0, 24(sp)
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; RISCV32-NEXT: call __multi3@plt
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; RISCV32-NEXT: mul a0, s8, s7
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; RISCV32-NEXT: mul a1, s3, s0
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; RISCV32-NEXT: add a0, a1, a0
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; RISCV32-NEXT: mulhu a5, s7, s0
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; RISCV32-NEXT: add a0, a5, a0
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; RISCV32-NEXT: mul a1, s5, s6
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; RISCV32-NEXT: mul a2, s2, s1
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; RISCV32-NEXT: add a1, a2, a1
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; RISCV32-NEXT: mulhu t0, s6, s1
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; RISCV32-NEXT: add t1, t0, a1
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; RISCV32-NEXT: add a6, t1, a0
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; RISCV32-NEXT: mul a1, s7, s0
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; RISCV32-NEXT: mul a3, s6, s1
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; RISCV32-NEXT: add a4, a3, a1
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; RISCV32-NEXT: lw a1, 52(sp)
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; RISCV32-NEXT: lw a2, 48(sp)
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; RISCV32-NEXT: sltu a3, a4, a3
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; RISCV32-NEXT: add a3, a6, a3
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; RISCV32-NEXT: add a3, a1, a3
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; RISCV32-NEXT: add a6, a2, a4
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; RISCV32-NEXT: sltu a2, a6, a2
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; RISCV32-NEXT: add a7, a3, a2
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; RISCV32-NEXT: beq a7, a1, .LBB0_2
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; RISCV32-NEXT: # %bb.1: # %start
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; RISCV32-NEXT: sltu a2, a7, a1
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; RISCV32-NEXT: .LBB0_2: # %start
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; RISCV32-NEXT: sltu a0, a0, a5
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; RISCV32-NEXT: snez a1, s8
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; RISCV32-NEXT: snez a3, s3
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; RISCV32-NEXT: and a1, a3, a1
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; RISCV32-NEXT: mulhu a3, s3, s0
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; RISCV32-NEXT: snez a3, a3
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; RISCV32-NEXT: or a1, a1, a3
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; RISCV32-NEXT: mulhu a3, s8, s7
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; RISCV32-NEXT: snez a3, a3
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; RISCV32-NEXT: or a1, a1, a3
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; RISCV32-NEXT: or a0, a1, a0
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; RISCV32-NEXT: sltu a1, t1, t0
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; RISCV32-NEXT: snez a3, s5
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; RISCV32-NEXT: snez a4, s2
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; RISCV32-NEXT: and a3, a4, a3
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; RISCV32-NEXT: mulhu a4, s2, s1
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; RISCV32-NEXT: snez a4, a4
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; RISCV32-NEXT: or a3, a3, a4
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; RISCV32-NEXT: mulhu a4, s5, s6
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; RISCV32-NEXT: snez a4, a4
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; RISCV32-NEXT: or a3, a3, a4
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; RISCV32-NEXT: or a1, a3, a1
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; RISCV32-NEXT: or a3, s7, s3
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; RISCV32-NEXT: snez a3, a3
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; RISCV32-NEXT: or a4, s6, s2
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; RISCV32-NEXT: snez a4, a4
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; RISCV32-NEXT: and a3, a4, a3
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; RISCV32-NEXT: or a1, a3, a1
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; RISCV32-NEXT: or a0, a1, a0
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; RISCV32-NEXT: lw a1, 44(sp)
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; RISCV32-NEXT: lw a3, 40(sp)
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; RISCV32-NEXT: or a0, a0, a2
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; RISCV32-NEXT: andi a0, a0, 1
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; RISCV32-NEXT: sw a1, 4(s4)
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; RISCV32-NEXT: sw a3, 0(s4)
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; RISCV32-NEXT: sw a6, 8(s4)
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; RISCV32-NEXT: sw a7, 12(s4)
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; RISCV32-NEXT: sb a0, 16(s4)
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; RISCV32-NEXT: lw s8, 56(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s7, 60(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s6, 64(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s5, 68(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s4, 72(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s3, 76(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s2, 80(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s1, 84(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
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; RISCV32-NEXT: addi sp, sp, 96
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; RISCV32-NEXT: ret
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start:
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%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
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%1 = extractvalue { i128, i1 } %0, 0
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%2 = extractvalue { i128, i1 } %0, 1
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%3 = zext i1 %2 to i8
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%4 = insertvalue { i128, i8 } undef, i128 %1, 0
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%5 = insertvalue { i128, i8 } %4, i8 %3, 1
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ret { i128, i8 } %5
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}
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; Function Attrs: nounwind readnone speculatable
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declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { nounwind }
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