450 lines
13 KiB
LLVM
450 lines
13 KiB
LLVM
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Stackmap Header: no constants - 6 callsites
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; CHECK: .section .llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; Header
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; Num Functions
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; CHECK-NEXT: .long 8
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; Num Constants
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; CHECK-NEXT: .long 0
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; Num Callsites
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; CHECK-NEXT: .long 8
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; Functions and stack size
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; CHECK-NEXT: .quad test
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access1
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access2
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; CHECK-NEXT: .quad 168
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access3
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; CHECK-NEXT: .quad 168
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad anyreg_test1
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad anyreg_test2
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad patchpoint_spilldef
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; CHECK-NEXT: .quad 168
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad patchpoint_spillargs
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; CHECK-NEXT: .quad 192
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; CHECK-NEXT: .quad 1
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; No constants
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; Callsites
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; test
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; CHECK: .long .L{{.*}}-test
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; CHECK-NEXT: .short 0
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; 3 locations
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; CHECK-NEXT: .short 3
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; Loc 0: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 2: Constant 3
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 3
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define i64 @test() nounwind ssp uwtable {
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entry:
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call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 14, i8* null, i32 2, i32 1, i32 2, i64 3)
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ret i64 0
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}
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; property access 1 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK: .long .L{{.*}}-property_access1
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 14, i8* %f, i32 1, i8* %obj)
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ret i64 %ret
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}
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; property access 2 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK: .long .L{{.*}}-property_access2
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @property_access2() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, i8* %f, i32 1, i64* %obj)
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ret i64 %ret
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}
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; property access 3 - %obj is a frame index
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; CHECK: .long .L{{.*}}-property_access3
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Direct %r15 + 160
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 15
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 160
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define i64 @property_access3() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 14, i8* %f, i32 0, i64* %obj)
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ret i64 %ret
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}
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; anyreg_test1
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; CHECK: .long .L{{.*}}-anyreg_test1
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; CHECK-NEXT: .short 0
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; 13 locations
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; CHECK-NEXT: .short 13
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 12: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 14, i8* %f, i32 12, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
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ret i64 %ret
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}
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; anyreg_test2
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; CHECK: .long .L{{.*}}-anyreg_test2
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; CHECK-NEXT: .short 0
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; 13 locations
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; CHECK-NEXT: .short 13
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
; Loc 12: Register
|
||
|
|
; CHECK-NEXT: .byte 1
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
|
||
|
|
entry:
|
||
|
|
%f = inttoptr i64 12297829382473034410 to i8*
|
||
|
|
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
|
||
|
|
ret i64 %ret
|
||
|
|
}
|
||
|
|
|
||
|
|
; Test spilling the return value of an anyregcc call.
|
||
|
|
;
|
||
|
|
; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
|
||
|
|
;
|
||
|
|
; CHECK: .long .L{{.*}}-patchpoint_spilldef
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .short 3
|
||
|
|
; Loc 0: Register (some register that will be spilled to the stack)
|
||
|
|
; CHECK-NEXT: .byte 1
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
; Loc 1: Register %r2
|
||
|
|
; CHECK-NEXT: .byte 1
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short 2
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
; Loc 1: Register %r3
|
||
|
|
; CHECK-NEXT: .byte 1
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short 3
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
|
||
|
|
entry:
|
||
|
|
%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
|
||
|
|
tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
|
||
|
|
ret i64 %result
|
||
|
|
}
|
||
|
|
|
||
|
|
; Test spilling the arguments of an anyregcc call.
|
||
|
|
;
|
||
|
|
; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
|
||
|
|
;
|
||
|
|
; CHECK: .long .L{{.*}}-patchpoint_spillargs
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .short 5
|
||
|
|
; Loc 0: Return a register
|
||
|
|
; CHECK-NEXT: .byte 1
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
; Loc 1: Arg0 in a Register
|
||
|
|
; CHECK-NEXT: .byte 1
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
; Loc 2: Arg1 in a Register
|
||
|
|
; CHECK-NEXT: .byte 1
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short {{[0-9]+}}
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long 0
|
||
|
|
; Loc 3: Arg2 spilled to %r15 +
|
||
|
|
; CHECK-NEXT: .byte 3
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short 15
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long
|
||
|
|
; Loc 4: Arg3 spilled to %r15 +
|
||
|
|
; CHECK-NEXT: .byte 3
|
||
|
|
; CHECK-NEXT: .byte 0
|
||
|
|
; CHECK-NEXT: .short 8
|
||
|
|
; CHECK-NEXT: .short 15
|
||
|
|
; CHECK-NEXT: .short 0
|
||
|
|
; CHECK-NEXT: .long
|
||
|
|
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
|
||
|
|
entry:
|
||
|
|
tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
|
||
|
|
%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
|
||
|
|
ret i64 %result
|
||
|
|
}
|
||
|
|
|
||
|
|
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
|
||
|
|
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
|