134 lines
3.1 KiB
LLVM
134 lines
3.1 KiB
LLVM
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; Test 31-to-64 bit zero extensions.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test register extension, starting with an i64.
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define i64 @f1(i64 %a) {
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; CHECK-LABEL: f1:
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; CHECK: llgtr %r2, %r2
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; CHECK: br %r14
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%ext = and i64 %a, 2147483647
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ret i64 %ext
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}
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; Test register extension, starting with an i32.
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define i64 @f2(i32 %a) {
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; CHECK-LABEL: f2:
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; CHECK: llgtr %r2, %r2
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; CHECK: br %r14
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%and = and i32 %a, 2147483647
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; ... and the other way around.
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define i64 @f3(i32 %a) {
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; CHECK-LABEL: f3:
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; CHECK: llgtr %r2, %r2
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; CHECK: br %r14
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%ext = zext i32 %a to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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; Check LLGT with no displacement.
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define i64 @f4(i32 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: llgt %r2, 0(%r2)
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; CHECK: br %r14
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%word = load i32, i32 *%src
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%ext = zext i32 %word to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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; ... and the other way around.
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define i64 @f5(i32 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: llgt %r2, 0(%r2)
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; CHECK: br %r14
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%word = load i32, i32 *%src
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%and = and i32 %word, 2147483647
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%ext = zext i32 %and to i64
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ret i64 %ext
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}
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; Check the high end of the LLGT range.
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define i64 @f6(i32 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: llgt %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%word = load i32, i32 *%ptr
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%ext = zext i32 %word to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i32 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r2, 524288
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; CHECK: llgt %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%word = load i32, i32 *%ptr
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%ext = zext i32 %word to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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; Check the high end of the negative LLGT range.
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define i64 @f8(i32 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: llgt %r2, -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%word = load i32, i32 *%ptr
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%ext = zext i32 %word to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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; Check the low end of the LLGT range.
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define i64 @f9(i32 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: llgt %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%word = load i32, i32 *%ptr
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%ext = zext i32 %word to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f10(i32 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r2, -524292
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; CHECK: llgt %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%word = load i32, i32 *%ptr
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%ext = zext i32 %word to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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; Check that LLGT allows an index.
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define i64 @f11(i64 %src, i64 %index) {
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; CHECK-LABEL: f11:
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; CHECK: llgt %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%word = load i32, i32 *%ptr
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%ext = zext i32 %word to i64
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%and = and i64 %ext, 2147483647
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ret i64 %and
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}
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