254 lines
7.6 KiB
LLVM
254 lines
7.6 KiB
LLVM
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; Test 32-bit addition in which the second operand is a sign-extended
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; i16 memory value.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @foo()
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; Check the low end of the AH range.
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define zeroext i1 @f1(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f1:
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; CHECK: ah %r3, 0(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%half = load i16, i16 *%src
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the high end of the aligned AH range.
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define zeroext i1 @f2(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f2:
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; CHECK: ah %r3, 4094(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 2047
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the next halfword up, which should use AHY instead of AH.
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define zeroext i1 @f3(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f3:
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; CHECK: ahy %r3, 4096(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 2048
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the high end of the aligned AHY range.
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define zeroext i1 @f4(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f4:
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; CHECK: ahy %r3, 524286(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 262143
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f5(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f5:
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; CHECK: agfi %r4, 524288
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; CHECK: ah %r3, 0(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 262144
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the high end of the negative aligned AHY range.
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define zeroext i1 @f6(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f6:
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; CHECK: ahy %r3, -2(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -1
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the low end of the AHY range.
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define zeroext i1 @f7(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f7:
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; CHECK: ahy %r3, -524288(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -262144
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f8(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r4, -524290
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; CHECK: ah %r3, 0(%r4)
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; CHECK-DAG: st %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%src, i64 -262145
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check that AH allows an index.
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define zeroext i1 @f9(i64 %src, i64 %index, i32 %a, i32 *%res) {
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; CHECK-LABEL: f9:
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; CHECK: ah %r4, 4094({{%r3,%r2|%r2,%r3}})
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; CHECK-DAG: st %r4, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4094
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%ptr = inttoptr i64 %add2 to i16 *
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check that AHY allows an index.
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define zeroext i1 @f10(i64 %src, i64 %index, i32 %a, i32 *%res) {
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; CHECK-LABEL: f10:
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; CHECK: ahy %r4, 4096({{%r3,%r2|%r2,%r3}})
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; CHECK-DAG: st %r4, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: afi [[REG]], 1342177280
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 33
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i16 *
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%half = load i16, i16 *%ptr
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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ret i1 %obit
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}
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; Check using the overflow result for a branch.
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define void @f11(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f11:
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; CHECK: ah %r3, 0(%r4)
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; CHECK: st %r3, 0(%r5)
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; CHECK: jgo foo@PLT
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; CHECK: br %r14
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%half = load i16, i16 *%src
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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br i1 %obit, label %call, label %exit
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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define void @f12(i32 %dummy, i32 %a, i16 *%src, i32 *%res) {
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; CHECK-LABEL: f12:
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; CHECK: ah %r3, 0(%r4)
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; CHECK: st %r3, 0(%r5)
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; CHECK: jgno foo@PLT
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; CHECK: br %r14
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%half = load i16, i16 *%src
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%b = sext i16 %half to i32
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%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue {i32, i1} %t, 0
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%obit = extractvalue {i32, i1} %t, 1
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store i32 %val, i32 *%res
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br i1 %obit, label %exit, label %call
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call:
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tail call i32 @foo()
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br label %exit
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exit:
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ret void
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}
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declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
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