47 lines
1.8 KiB
LLVM
47 lines
1.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | FileCheck %s
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; PR1877
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@NNTOT = weak global i32 0 ; <i32*> [#uses=1]
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@G = weak global float 0.000000e+00 ; <float*> [#uses=1]
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define void @runcont(i32* %source) nounwind {
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; CHECK-LABEL: runcont:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl L_NNTOT$non_lazy_ptr, %ecx
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; CHECK-NEXT: movl (%ecx), %ecx
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; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB0_1: ## %bb
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vcvtsi2ssl (%eax,%edx,4), %xmm2, %xmm1
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; CHECK-NEXT: vaddss %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: incl %edx
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; CHECK-NEXT: cmpl %edx, %ecx
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; CHECK-NEXT: jne LBB0_1
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; CHECK-NEXT: ## %bb.2: ## %bb13
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; CHECK-NEXT: movl L_G$non_lazy_ptr, %eax
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; CHECK-NEXT: vmovss %xmm0, (%eax)
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; CHECK-NEXT: retl
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entry:
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%tmp10 = load i32, i32* @NNTOT, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %entry
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%neuron.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
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%thesum.0 = phi float [ 0.000000e+00, %entry ], [ %tmp6, %bb ] ; <float> [#uses=1]
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%tmp2 = getelementptr i32, i32* %source, i32 %neuron.0 ; <i32*> [#uses=1]
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%tmp3 = load i32, i32* %tmp2, align 4 ; <i32> [#uses=1]
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%tmp34 = sitofp i32 %tmp3 to float ; <float> [#uses=1]
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%tmp6 = fadd float %tmp34, %thesum.0 ; <float> [#uses=2]
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%indvar.next = add i32 %neuron.0, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %indvar.next, %tmp10 ; <i1> [#uses=1]
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br i1 %exitcond, label %bb13, label %bb
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bb13: ; preds = %bb
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store volatile float %tmp6, float* @G, align 4
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ret void
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}
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