194 lines
6.1 KiB
LLVM
194 lines
6.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2
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define i32 @shl48sar47(i64 %a) #0 {
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; CHECK-LABEL: shl48sar47:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movswq %di, %rax
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; CHECK-NEXT: addl %eax, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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%1 = shl i64 %a, 48
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%2 = ashr exact i64 %1, 47
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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define i32 @shl48sar49(i64 %a) #0 {
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; CHECK-LABEL: shl48sar49:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movswq %di, %rax
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; CHECK-NEXT: shrq %rax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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%1 = shl i64 %a, 48
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%2 = ashr exact i64 %1, 49
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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define i32 @shl56sar55(i64 %a) #0 {
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; CHECK-LABEL: shl56sar55:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movsbq %dil, %rax
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; CHECK-NEXT: addl %eax, %eax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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%1 = shl i64 %a, 56
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%2 = ashr exact i64 %1, 55
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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define i32 @shl56sar57(i64 %a) #0 {
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; CHECK-LABEL: shl56sar57:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movsbq %dil, %rax
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; CHECK-NEXT: shrq %rax
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; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
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; CHECK-NEXT: retq
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%1 = shl i64 %a, 56
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%2 = ashr exact i64 %1, 57
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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define i8 @all_sign_bit_ashr(i8 %x) {
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; CHECK-LABEL: all_sign_bit_ashr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: andb $1, %al
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; CHECK-NEXT: negb %al
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%and = and i8 %x, 1
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%neg = sub i8 0, %and
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%sar = ashr i8 %neg, 6
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ret i8 %sar
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}
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define <4 x i32> @all_sign_bit_ashr_vec0(<4 x i32> %x) {
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; SSE-LABEL: all_sign_bit_ashr_vec0:
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; SSE: # %bb.0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: all_sign_bit_ashr_vec0:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: all_sign_bit_ashr_vec0:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX2-NEXT: retq
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%and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>
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%neg = sub <4 x i32> zeroinitializer, %and
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%sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0>
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ret <4 x i32> %sar
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}
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define <4 x i32> @all_sign_bit_ashr_vec1(<4 x i32> %x) {
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; SSE-LABEL: all_sign_bit_ashr_vec1:
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; SSE: # %bb.0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,0,0]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: all_sign_bit_ashr_vec1:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: all_sign_bit_ashr_vec1:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
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; AVX2-NEXT: retq
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%and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>
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%sub = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %and
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%shf = shufflevector <4 x i32> %sub, <4 x i32> undef, <4 x i32> zeroinitializer
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%sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0>
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ret <4 x i32> %sar
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}
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define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) {
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; SSE-LABEL: all_sign_bit_ashr_vec2:
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; SSE: # %bb.0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: paddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: all_sign_bit_ashr_vec2:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: all_sign_bit_ashr_vec2:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>
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%add = add <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
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%sar = ashr <4 x i32> %add, <i32 1, i32 31, i32 5, i32 0>
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ret <4 x i32> %sar
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}
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define <4 x i32> @all_sign_bit_ashr_vec3(<4 x i32> %x) {
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; SSE-LABEL: all_sign_bit_ashr_vec3:
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; SSE: # %bb.0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,0,0]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: all_sign_bit_ashr_vec3:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: all_sign_bit_ashr_vec3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1]
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
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; AVX2-NEXT: retq
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%and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1>
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%add = add <4 x i32> %and, <i32 -1, i32 1, i32 2, i32 3>
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%shf = shufflevector <4 x i32> %add, <4 x i32> undef, <4 x i32> zeroinitializer
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%sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0>
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ret <4 x i32> %sar
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}
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attributes #0 = { nounwind }
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