121 lines
4.5 KiB
LLVM
121 lines
4.5 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
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;PR29079
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define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) {
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; X32-SSE-LABEL: mask_ucvt_4i32_4f32:
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; X32-SSE: # %bb.0:
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; X32-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X32-AVX-LABEL: mask_ucvt_4i32_4f32:
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; X32-AVX: # %bb.0:
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; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0
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; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X32-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: mask_ucvt_4i32_4f32:
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; X64-SSE: # %bb.0:
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; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: mask_ucvt_4i32_4f32:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X64-AVX-NEXT: retq
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%and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
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%cvt = uitofp <4 x i32> %and to <4 x float>
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ret <4 x float> %cvt
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}
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define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {
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; X32-SSE-LABEL: mask_ucvt_4i32_4f64:
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; X32-SSE: # %bb.0:
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm1
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; X32-SSE-NEXT: movaps %xmm2, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X32-AVX-LABEL: mask_ucvt_4i32_4f64:
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; X32-AVX: # %bb.0:
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; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0
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; X32-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
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; X32-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: mask_ucvt_4i32_4f64:
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; X64-SSE: # %bb.0:
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; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
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; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm1
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; X64-SSE-NEXT: movaps %xmm2, %xmm0
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: mask_ucvt_4i32_4f64:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
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; X64-AVX-NEXT: retq
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%and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
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%cvt = uitofp <4 x i32> %and to <4 x double>
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ret <4 x double> %cvt
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}
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; Regression noticed in D56387
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define <4 x float> @lshr_truncate_mask_ucvt_4i64_4f32(<4 x i64> *%p0) {
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; X32-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
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; X32-SSE: # %bb.0:
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; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: movups (%eax), %xmm0
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; X32-SSE-NEXT: movups 16(%eax), %xmm1
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; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; X32-SSE-NEXT: psrld $16, %xmm0
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; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; X32-SSE-NEXT: mulps {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X32-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
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; X32-AVX: # %bb.0:
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; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-AVX-NEXT: vmovups (%eax), %xmm0
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; X32-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2]
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; X32-AVX-NEXT: vpsrld $16, %xmm0, %xmm0
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; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X32-AVX-NEXT: vmulps {{\.LCPI.*}}, %xmm0, %xmm0
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; X32-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
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; X64-SSE: # %bb.0:
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; X64-SSE-NEXT: movups (%rdi), %xmm0
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; X64-SSE-NEXT: movups 16(%rdi), %xmm1
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; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; X64-SSE-NEXT: psrld $16, %xmm0
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; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; X64-SSE-NEXT: mulps {{.*}}(%rip), %xmm0
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: vmovups (%rdi), %xmm0
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; X64-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2]
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; X64-AVX-NEXT: vpsrld $16, %xmm0, %xmm0
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; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X64-AVX-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: retq
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%load = load <4 x i64>, <4 x i64>* %p0, align 2
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%lshr = lshr <4 x i64> %load, <i64 16, i64 16, i64 16, i64 16>
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%and = and <4 x i64> %lshr, <i64 65535, i64 65535, i64 65535, i64 65535>
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%uitofp = uitofp <4 x i64> %and to <4 x float>
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%fmul = fmul <4 x float> %uitofp, <float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000, float 0x3EF0001000000000>
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ret <4 x float> %fmul
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}
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