467 lines
17 KiB
C++
467 lines
17 KiB
C++
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//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../Common/AssemblerUtils.h"
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#include "LlvmState.h"
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#include "MCInstrDescView.h"
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#include "ParallelSnippetGenerator.h"
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#include "RegisterAliasing.h"
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#include "SerialSnippetGenerator.h"
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#include "TestBase.h"
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#include "X86InstrInfo.h"
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#include <unordered_set>
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namespace llvm {
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namespace exegesis {
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void InitializeX86ExegesisTarget();
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namespace {
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using testing::AnyOf;
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using testing::ElementsAre;
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using testing::Gt;
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using testing::HasSubstr;
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using testing::Not;
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using testing::SizeIs;
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using testing::UnorderedElementsAre;
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MATCHER(IsInvalid, "") { return !arg.isValid(); }
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MATCHER(IsReg, "") { return arg.isReg(); }
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class X86SnippetGeneratorTest : public X86TestBase {
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protected:
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X86SnippetGeneratorTest() : InstrInfo(State.getInstrInfo()) {}
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const MCInstrInfo &InstrInfo;
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};
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template <typename SnippetGeneratorT>
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class SnippetGeneratorTest : public X86SnippetGeneratorTest {
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protected:
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SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
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std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
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randomGenerator().seed(0); // Initialize seed.
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const Instruction &Instr = State.getIC().getInstr(Opcode);
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auto CodeTemplateOrError = Generator.generateCodeTemplates(
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&Instr, State.getRATC().emptyRegisters());
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EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
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return std::move(CodeTemplateOrError.get());
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}
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SnippetGeneratorT Generator;
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};
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using SerialSnippetGeneratorTest = SnippetGeneratorTest<SerialSnippetGenerator>;
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using ParallelSnippetGeneratorTest =
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SnippetGeneratorTest<ParallelSnippetGenerator>;
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TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
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// - ADC16i16
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// - Op0 Explicit Use Immediate
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// - Op1 Implicit Def Reg(AX)
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// - Op2 Implicit Def Reg(EFLAGS)
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// - Op3 Implicit Use Reg(AX)
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// - Op4 Implicit Use Reg(EFLAGS)
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// - Var0 [Op0]
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// - hasAliasingImplicitRegisters (execution is always serial)
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// - hasAliasingRegisters
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const unsigned Opcode = X86::ADC16i16;
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EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX);
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EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS);
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EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], X86::AX);
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EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS);
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
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EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
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}
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TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
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// - ADD16ri
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// - Op0 Explicit Def RegClass(GR16)
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// - Op1 Explicit Use RegClass(GR16) TiedToOp0
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// - Op2 Explicit Use Immediate
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// - Op3 Implicit Def Reg(EFLAGS)
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// - Var0 [Op0,Op1]
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// - Var1 [Op2]
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// - hasTiedRegisters (execution is always serial)
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// - hasAliasingRegisters
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const unsigned Opcode = X86::ADD16ri;
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EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS);
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
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EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
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EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
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}
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TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
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// - VXORPSrr
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// - Op0 Explicit Def RegClass(VR128)
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// - Op1 Explicit Use RegClass(VR128)
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// - Op2 Explicit Use RegClass(VR128)
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasAliasingRegisters
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const unsigned Opcode = X86::VXORPSrr;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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EXPECT_THAT(IT.getVariableValues(),
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AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
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ElementsAre(IsReg(), IsReg(), IsInvalid())))
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<< "Op0 is either set to Op1 or to Op2";
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}
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TEST_F(SerialSnippetGeneratorTest,
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ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
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// - VXORPSrr
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// - Op0 Explicit Def RegClass(VR128)
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// - Op1 Explicit Use RegClass(VR128)
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// - Op2 Explicit Use RegClass(VR128)
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - hasAliasingRegisters
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const unsigned Opcode = X86::VXORPSrr;
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randomGenerator().seed(0); // Initialize seed.
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const Instruction &Instr = State.getIC().getInstr(Opcode);
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auto AllRegisters = State.getRATC().emptyRegisters();
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AllRegisters.flip();
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auto Error =
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Generator.generateCodeTemplates(&Instr, AllRegisters).takeError();
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EXPECT_TRUE((bool)Error);
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consumeError(std::move(Error));
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}
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TEST_F(SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) {
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// - CMP64rr
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// - Op0 Explicit Use RegClass(GR64)
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// - Op1 Explicit Use RegClass(GR64)
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// - Op2 Implicit Def Reg(EFLAGS)
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// - Var0 [Op0]
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// - Var1 [Op1]
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const unsigned Opcode = X86::CMP64rr;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
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for (const auto &CT : CodeTemplates) {
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EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
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ASSERT_THAT(CT.Instructions, SizeIs(2));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
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EXPECT_THAT(IT.getVariableValues(),
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AnyOf(ElementsAre(IsReg(), IsInvalid()),
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ElementsAre(IsInvalid(), IsReg())));
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EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
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// TODO: check that the two instructions alias each other.
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}
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}
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TEST_F(SerialSnippetGeneratorTest, LAHF) {
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// - LAHF
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// - Op0 Implicit Def Reg(AH)
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// - Op1 Implicit Use Reg(EFLAGS)
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const unsigned Opcode = X86::LAHF;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
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for (const auto &CT : CodeTemplates) {
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EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
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ASSERT_THAT(CT.Instructions, SizeIs(2));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
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}
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}
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TEST_F(SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
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// - VCVTUSI642SDZrrb_Int
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// - Op0 Explicit Def RegClass(VR128X)
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// - Op1 Explicit Use RegClass(VR128X)
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// - Op2 Explicit Use STATIC_ROUNDING
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// - Op2 Explicit Use RegClass(GR64)
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// - Op4 Implicit Use Reg(MXSCR)
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const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
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const Instruction &Instr = State.getIC().getInstr(Opcode);
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std::vector<BenchmarkCode> Configs;
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auto Error = Generator.generateConfigurations(
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&Instr, Configs, State.getRATC().emptyRegisters());
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ASSERT_FALSE(Error);
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ASSERT_THAT(Configs, SizeIs(1));
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const BenchmarkCode &BC = Configs[0];
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ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
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ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
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}
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TEST_F(ParallelSnippetGeneratorTest, ParallelInstruction) {
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// - BNDCL32rr
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// - Op0 Explicit Use RegClass(BNDR)
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// - Op1 Explicit Use RegClass(GR32)
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// - Var0 [Op0]
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// - Var1 [Op1]
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const unsigned Opcode = X86::BNDCL32rr;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Info, HasSubstr("parallel"));
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EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
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EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
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EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
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}
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TEST_F(ParallelSnippetGeneratorTest, SerialInstruction) {
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// - CDQ
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// - Op0 Implicit Def Reg(EAX)
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// - Op1 Implicit Def Reg(EDX)
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// - Op2 Implicit Use Reg(EAX)
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// - hasAliasingImplicitRegisters (execution is always serial)
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// - hasAliasingRegisters
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const unsigned Opcode = X86::CDQ;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Info, HasSubstr("serial"));
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EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
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}
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TEST_F(ParallelSnippetGeneratorTest, StaticRenaming) {
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// CMOV32rr has tied variables, we enumerate the possible values to execute
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// as many in parallel as possible.
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// - CMOV32rr
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// - Op0 Explicit Def RegClass(GR32)
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// - Op1 Explicit Use RegClass(GR32) TiedToOp0
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// - Op2 Explicit Use RegClass(GR32)
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// - Op3 Explicit Use Immediate
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// - Op3 Implicit Use Reg(EFLAGS)
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// - Var0 [Op0,Op1]
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// - Var1 [Op2]
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// - hasTiedRegisters (execution is always serial)
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// - hasAliasingRegisters
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const unsigned Opcode = X86::CMOV32rr;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Info, HasSubstr("static renaming"));
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EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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constexpr const unsigned kInstructionCount = 15;
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ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
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std::unordered_set<unsigned> AllDefRegisters;
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for (const auto &IT : CT.Instructions) {
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ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
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AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
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}
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EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
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<< "Each instruction writes to a different register";
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}
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TEST_F(ParallelSnippetGeneratorTest, NoTiedVariables) {
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// CMOV_GR32 has no tied variables, we make sure def and use are different
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// from each other.
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// - CMOV_GR32
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// - Op0 Explicit Def RegClass(GR32)
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// - Op1 Explicit Use RegClass(GR32)
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// - Op2 Explicit Use RegClass(GR32)
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// - Op3 Explicit Use Immediate
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// - Op4 Implicit Use Reg(EFLAGS)
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// - Var0 [Op0]
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// - Var1 [Op1]
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// - Var2 [Op2]
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// - Var3 [Op3]
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// - hasAliasingRegisters
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const unsigned Opcode = X86::CMOV_GR32;
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const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
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ASSERT_THAT(CodeTemplates, SizeIs(1));
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const auto &CT = CodeTemplates[0];
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EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
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EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
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ASSERT_THAT(CT.Instructions, SizeIs(1));
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const InstructionTemplate &IT = CT.Instructions[0];
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EXPECT_THAT(IT.getOpcode(), Opcode);
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ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
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EXPECT_THAT(IT.getVariableValues()[0].getReg(),
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Not(IT.getVariableValues()[1].getReg()))
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<< "Def is different from first Use";
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EXPECT_THAT(IT.getVariableValues()[0].getReg(),
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Not(IT.getVariableValues()[2].getReg()))
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<< "Def is different from second Use";
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EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
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}
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TEST_F(ParallelSnippetGeneratorTest, MemoryUse) {
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// Mov32rm reads from memory.
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// - MOV32rm
|
||
|
|
// - Op0 Explicit Def RegClass(GR32)
|
||
|
|
// - Op1 Explicit Use Memory RegClass(GR8)
|
||
|
|
// - Op2 Explicit Use Memory
|
||
|
|
// - Op3 Explicit Use Memory RegClass(GRH8)
|
||
|
|
// - Op4 Explicit Use Memory
|
||
|
|
// - Op5 Explicit Use Memory RegClass(SEGMENT_REG)
|
||
|
|
// - Var0 [Op0]
|
||
|
|
// - Var1 [Op1]
|
||
|
|
// - Var2 [Op2]
|
||
|
|
// - Var3 [Op3]
|
||
|
|
// - Var4 [Op4]
|
||
|
|
// - Var5 [Op5]
|
||
|
|
// - hasMemoryOperands
|
||
|
|
// - hasAliasingRegisters
|
||
|
|
const unsigned Opcode = X86::MOV32rm;
|
||
|
|
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||
|
|
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||
|
|
const auto &CT = CodeTemplates[0];
|
||
|
|
EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
|
||
|
|
EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
|
||
|
|
ASSERT_THAT(CT.Instructions,
|
||
|
|
SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
|
||
|
|
const InstructionTemplate &IT = CT.Instructions[0];
|
||
|
|
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||
|
|
ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
|
||
|
|
EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
|
||
|
|
EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
|
||
|
|
EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
|
||
|
|
EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(ParallelSnippetGeneratorTest, MOV16ms) {
|
||
|
|
const unsigned Opcode = X86::MOV16ms;
|
||
|
|
const Instruction &Instr = State.getIC().getInstr(Opcode);
|
||
|
|
std::vector<BenchmarkCode> Benchmarks;
|
||
|
|
auto Err = Generator.generateConfigurations(&Instr, Benchmarks,
|
||
|
|
State.getRATC().emptyRegisters());
|
||
|
|
EXPECT_TRUE((bool)Err);
|
||
|
|
EXPECT_THAT(toString(std::move(Err)),
|
||
|
|
testing::HasSubstr("no available registers"));
|
||
|
|
}
|
||
|
|
|
||
|
|
class FakeSnippetGenerator : public SnippetGenerator {
|
||
|
|
public:
|
||
|
|
FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
|
||
|
|
: SnippetGenerator(State, Opts) {}
|
||
|
|
|
||
|
|
const Instruction &getInstr(unsigned Opcode) {
|
||
|
|
return State.getIC().getInstr(Opcode);
|
||
|
|
}
|
||
|
|
|
||
|
|
InstructionTemplate getInstructionTemplate(unsigned Opcode) {
|
||
|
|
return {&getInstr(Opcode)};
|
||
|
|
}
|
||
|
|
|
||
|
|
private:
|
||
|
|
Expected<std::vector<CodeTemplate>>
|
||
|
|
generateCodeTemplates(InstructionTemplate, const BitVector &) const override {
|
||
|
|
return make_error<StringError>("not implemented", inconvertibleErrorCode());
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeSnippetGenerator>;
|
||
|
|
|
||
|
|
testing::Matcher<const RegisterValue &> IsRegisterValue(unsigned Reg,
|
||
|
|
APInt Value) {
|
||
|
|
return testing::AllOf(testing::Field(&RegisterValue::Register, Reg),
|
||
|
|
testing::Field(&RegisterValue::Value, Value));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(FakeSnippetGeneratorTest, MemoryUse_Movsb) {
|
||
|
|
// MOVSB writes to scratch memory register.
|
||
|
|
// - MOVSB
|
||
|
|
// - Op0 Explicit Use Memory RegClass(GR8)
|
||
|
|
// - Op1 Explicit Use Memory RegClass(GR8)
|
||
|
|
// - Op2 Explicit Use Memory RegClass(SEGMENT_REG)
|
||
|
|
// - Op3 Implicit Def Reg(EDI)
|
||
|
|
// - Op4 Implicit Def Reg(ESI)
|
||
|
|
// - Op5 Implicit Use Reg(EDI)
|
||
|
|
// - Op6 Implicit Use Reg(ESI)
|
||
|
|
// - Op7 Implicit Use Reg(DF)
|
||
|
|
// - Var0 [Op0]
|
||
|
|
// - Var1 [Op1]
|
||
|
|
// - Var2 [Op2]
|
||
|
|
// - hasMemoryOperands
|
||
|
|
// - hasAliasingImplicitRegisters (execution is always serial)
|
||
|
|
// - hasAliasingRegisters
|
||
|
|
const unsigned Opcode = X86::MOVSB;
|
||
|
|
const Instruction &Instr = State.getIC().getInstr(Opcode);
|
||
|
|
std::vector<BenchmarkCode> Benchmarks;
|
||
|
|
auto Error = Generator.generateConfigurations(
|
||
|
|
&Instr, Benchmarks, State.getRATC().emptyRegisters());
|
||
|
|
EXPECT_TRUE((bool)Error);
|
||
|
|
consumeError(std::move(Error));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
|
||
|
|
// ADD16ri:
|
||
|
|
// explicit def 0 : reg RegClass=GR16
|
||
|
|
// explicit use 1 : reg RegClass=GR16 | TIED_TO:0
|
||
|
|
// explicit use 2 : imm
|
||
|
|
// implicit def : EFLAGS
|
||
|
|
InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
|
||
|
|
IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
|
||
|
|
std::vector<InstructionTemplate> Snippet;
|
||
|
|
Snippet.push_back(std::move(IT));
|
||
|
|
const auto RIV = Generator.computeRegisterInitialValues(Snippet);
|
||
|
|
EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
|
||
|
|
// ADD64rr:
|
||
|
|
// mov64ri rax, 42
|
||
|
|
// add64rr rax, rax, rbx
|
||
|
|
// -> only rbx needs defining.
|
||
|
|
std::vector<InstructionTemplate> Snippet;
|
||
|
|
{
|
||
|
|
InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
|
||
|
|
Mov.getValueFor(Mov.getInstr().Variables[0]) =
|
||
|
|
MCOperand::createReg(X86::RAX);
|
||
|
|
Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
|
||
|
|
Snippet.push_back(std::move(Mov));
|
||
|
|
}
|
||
|
|
{
|
||
|
|
InstructionTemplate Add = Generator.getInstructionTemplate(X86::ADD64rr);
|
||
|
|
Add.getValueFor(Add.getInstr().Variables[0]) =
|
||
|
|
MCOperand::createReg(X86::RAX);
|
||
|
|
Add.getValueFor(Add.getInstr().Variables[1]) =
|
||
|
|
MCOperand::createReg(X86::RBX);
|
||
|
|
Snippet.push_back(std::move(Add));
|
||
|
|
}
|
||
|
|
|
||
|
|
const auto RIV = Generator.computeRegisterInitialValues(Snippet);
|
||
|
|
EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::RBX, APInt())));
|
||
|
|
}
|
||
|
|
|
||
|
|
} // namespace
|
||
|
|
} // namespace exegesis
|
||
|
|
} // namespace llvm
|