319 lines
11 KiB
C++
319 lines
11 KiB
C++
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//=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <iterator>
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#include <memory>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "packets"
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static cl::opt<unsigned> InstrLimit("dfa-instr-limit", cl::Hidden,
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cl::init(0), cl::desc("If present, stops packetizing after N instructions"));
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static unsigned InstrCount = 0;
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// Check if the resources occupied by a MCInstrDesc are available in the
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// current state.
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bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) {
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unsigned Action = ItinActions[MID->getSchedClass()];
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if (MID->getSchedClass() == 0 || Action == 0)
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return false;
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return A.canAdd(Action);
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}
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// Reserve the resources occupied by a MCInstrDesc and change the current
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// state to reflect that change.
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void DFAPacketizer::reserveResources(const MCInstrDesc *MID) {
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unsigned Action = ItinActions[MID->getSchedClass()];
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if (MID->getSchedClass() == 0 || Action == 0)
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return;
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A.add(Action);
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}
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// Check if the resources occupied by a machine instruction are available
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// in the current state.
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bool DFAPacketizer::canReserveResources(MachineInstr &MI) {
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const MCInstrDesc &MID = MI.getDesc();
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return canReserveResources(&MID);
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}
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// Reserve the resources occupied by a machine instruction and change the
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// current state to reflect that change.
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void DFAPacketizer::reserveResources(MachineInstr &MI) {
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const MCInstrDesc &MID = MI.getDesc();
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reserveResources(&MID);
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}
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unsigned DFAPacketizer::getUsedResources(unsigned InstIdx) {
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ArrayRef<NfaPath> NfaPaths = A.getNfaPaths();
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assert(!NfaPaths.empty() && "Invalid bundle!");
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const NfaPath &RS = NfaPaths.front();
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// RS stores the cumulative resources used up to and including the I'th
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// instruction. The 0th instruction is the base case.
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if (InstIdx == 0)
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return RS[0];
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// Return the difference between the cumulative resources used by InstIdx and
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// its predecessor.
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return RS[InstIdx] ^ RS[InstIdx - 1];
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}
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namespace llvm {
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// This class extends ScheduleDAGInstrs and overrides the schedule method
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// to build the dependence graph.
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class DefaultVLIWScheduler : public ScheduleDAGInstrs {
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private:
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AAResults *AA;
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/// Ordered list of DAG postprocessing steps.
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std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
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public:
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DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
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AAResults *AA);
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// Actual scheduling work.
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void schedule() override;
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/// DefaultVLIWScheduler takes ownership of the Mutation object.
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void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
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Mutations.push_back(std::move(Mutation));
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}
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protected:
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void postprocessDAG();
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};
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} // end namespace llvm
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DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
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MachineLoopInfo &MLI,
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AAResults *AA)
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: ScheduleDAGInstrs(MF, &MLI), AA(AA) {
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CanHandleTerminators = true;
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}
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/// Apply each ScheduleDAGMutation step in order.
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void DefaultVLIWScheduler::postprocessDAG() {
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for (auto &M : Mutations)
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M->apply(this);
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}
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void DefaultVLIWScheduler::schedule() {
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// Build the scheduling graph.
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buildSchedGraph(AA);
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postprocessDAG();
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}
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VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,
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MachineLoopInfo &mli, AAResults *aa)
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: MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
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ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
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ResourceTracker->setTrackResources(true);
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VLIWScheduler = new DefaultVLIWScheduler(MF, mli, AA);
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}
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VLIWPacketizerList::~VLIWPacketizerList() {
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delete VLIWScheduler;
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delete ResourceTracker;
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}
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// End the current packet, bundle packet instructions and reset DFA state.
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void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI) {
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LLVM_DEBUG({
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if (!CurrentPacketMIs.empty()) {
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dbgs() << "Finalizing packet:\n";
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unsigned Idx = 0;
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for (MachineInstr *MI : CurrentPacketMIs) {
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unsigned R = ResourceTracker->getUsedResources(Idx++);
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dbgs() << " * [res:0x" << utohexstr(R) << "] " << *MI;
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}
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}
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});
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if (CurrentPacketMIs.size() > 1) {
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MachineInstr &MIFirst = *CurrentPacketMIs.front();
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finalizeBundle(*MBB, MIFirst.getIterator(), MI.getInstrIterator());
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}
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CurrentPacketMIs.clear();
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ResourceTracker->clearResources();
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LLVM_DEBUG(dbgs() << "End packet\n");
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}
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// Bundle machine instructions into packets.
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void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator BeginItr,
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MachineBasicBlock::iterator EndItr) {
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assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
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VLIWScheduler->startBlock(MBB);
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VLIWScheduler->enterRegion(MBB, BeginItr, EndItr,
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std::distance(BeginItr, EndItr));
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VLIWScheduler->schedule();
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LLVM_DEBUG({
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dbgs() << "Scheduling DAG of the packetize region\n";
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VLIWScheduler->dump();
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});
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// Generate MI -> SU map.
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MIToSUnit.clear();
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for (SUnit &SU : VLIWScheduler->SUnits)
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MIToSUnit[SU.getInstr()] = &SU;
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bool LimitPresent = InstrLimit.getPosition();
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// The main packetizer loop.
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for (; BeginItr != EndItr; ++BeginItr) {
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if (LimitPresent) {
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if (InstrCount >= InstrLimit) {
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EndItr = BeginItr;
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break;
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}
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InstrCount++;
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}
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MachineInstr &MI = *BeginItr;
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initPacketizerState();
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// End the current packet if needed.
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if (isSoloInstruction(MI)) {
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endPacket(MBB, MI);
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continue;
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}
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// Ignore pseudo instructions.
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if (ignorePseudoInstruction(MI, MBB))
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continue;
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SUnit *SUI = MIToSUnit[&MI];
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assert(SUI && "Missing SUnit Info!");
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// Ask DFA if machine resource is available for MI.
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LLVM_DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI);
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bool ResourceAvail = ResourceTracker->canReserveResources(MI);
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LLVM_DEBUG({
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if (ResourceAvail)
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dbgs() << " Resources are available for adding MI to packet\n";
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else
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dbgs() << " Resources NOT available\n";
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});
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if (ResourceAvail && shouldAddToPacket(MI)) {
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// Dependency check for MI with instructions in CurrentPacketMIs.
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for (auto MJ : CurrentPacketMIs) {
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SUnit *SUJ = MIToSUnit[MJ];
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assert(SUJ && "Missing SUnit Info!");
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LLVM_DEBUG(dbgs() << " Checking against MJ " << *MJ);
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// Is it legal to packetize SUI and SUJ together.
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if (!isLegalToPacketizeTogether(SUI, SUJ)) {
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LLVM_DEBUG(dbgs() << " Not legal to add MI, try to prune\n");
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// Allow packetization if dependency can be pruned.
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if (!isLegalToPruneDependencies(SUI, SUJ)) {
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// End the packet if dependency cannot be pruned.
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LLVM_DEBUG(dbgs()
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<< " Could not prune dependencies for adding MI\n");
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endPacket(MBB, MI);
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break;
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}
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LLVM_DEBUG(dbgs() << " Pruned dependence for adding MI\n");
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}
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}
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} else {
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LLVM_DEBUG(if (ResourceAvail) dbgs()
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<< "Resources are available, but instruction should not be "
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"added to packet\n "
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<< MI);
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// End the packet if resource is not available, or if the instruction
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// shoud not be added to the current packet.
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endPacket(MBB, MI);
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}
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// Add MI to the current packet.
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LLVM_DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n');
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BeginItr = addToPacket(MI);
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} // For all instructions in the packetization range.
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// End any packet left behind.
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endPacket(MBB, EndItr);
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VLIWScheduler->exitRegion();
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VLIWScheduler->finishBlock();
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}
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bool VLIWPacketizerList::alias(const MachineMemOperand &Op1,
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const MachineMemOperand &Op2,
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bool UseTBAA) const {
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if (!Op1.getValue() || !Op2.getValue())
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return true;
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int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset());
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int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset;
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int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset;
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AliasResult AAResult =
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AA->alias(MemoryLocation(Op1.getValue(), Overlapa,
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UseTBAA ? Op1.getAAInfo() : AAMDNodes()),
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MemoryLocation(Op2.getValue(), Overlapb,
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UseTBAA ? Op2.getAAInfo() : AAMDNodes()));
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return AAResult != NoAlias;
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}
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bool VLIWPacketizerList::alias(const MachineInstr &MI1,
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const MachineInstr &MI2,
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bool UseTBAA) const {
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if (MI1.memoperands_empty() || MI2.memoperands_empty())
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return true;
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for (const MachineMemOperand *Op1 : MI1.memoperands())
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for (const MachineMemOperand *Op2 : MI2.memoperands())
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if (alias(*Op1, *Op2, UseTBAA))
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return true;
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return false;
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}
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// Add a DAG mutation object to the ordered list.
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void VLIWPacketizerList::addMutation(
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std::unique_ptr<ScheduleDAGMutation> Mutation) {
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VLIWScheduler->addMutation(std::move(Mutation));
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}
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