596 lines
21 KiB
C++
596 lines
21 KiB
C++
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//===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Analysis that tracks defined/used subregister lanes across COPY instructions
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/// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
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/// INSERT_SUBREG, EXTRACT_SUBREG).
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/// The information is used to detect dead definitions and the usage of
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/// (completely) undefined values and mark the operands as such.
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/// This pass is necessary because the dead/undef status is not obvious anymore
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/// when subregisters are involved.
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///
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/// Example:
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/// %0 = some definition
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/// %1 = IMPLICIT_DEF
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/// %2 = REG_SEQUENCE %0, sub0, %1, sub1
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/// %3 = EXTRACT_SUBREG %2, sub1
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/// = use %3
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/// The %0 definition is dead and %3 contains an undefined value.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/PassRegistry.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <deque>
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using namespace llvm;
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#define DEBUG_TYPE "detect-dead-lanes"
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namespace {
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/// Contains a bitmask of which lanes of a given virtual register are
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/// defined and which ones are actually used.
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struct VRegInfo {
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LaneBitmask UsedLanes;
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LaneBitmask DefinedLanes;
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};
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class DetectDeadLanes : public MachineFunctionPass {
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public:
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bool runOnMachineFunction(MachineFunction &MF) override;
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static char ID;
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DetectDeadLanes() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return "Detect Dead Lanes"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// Add used lane bits on the register used by operand \p MO. This translates
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/// the bitmask based on the operands subregister, and puts the register into
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/// the worklist if any new bits were added.
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void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
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/// Given a bitmask \p UsedLanes for the used lanes on a def output of a
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/// COPY-like instruction determine the lanes used on the use operands
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/// and call addUsedLanesOnOperand() for them.
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void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
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/// Given a use regiser operand \p Use and a mask of defined lanes, check
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/// if the operand belongs to a lowersToCopies() instruction, transfer the
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/// mask to the def and put the instruction into the worklist.
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void transferDefinedLanesStep(const MachineOperand &Use,
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LaneBitmask DefinedLanes);
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/// Given a mask \p DefinedLanes of lanes defined at operand \p OpNum
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/// of COPY-like instruction, determine which lanes are defined at the output
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/// operand \p Def.
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LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
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LaneBitmask DefinedLanes) const;
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/// Given a mask \p UsedLanes used from the output of instruction \p MI
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/// determine which lanes are used from operand \p MO of this instruction.
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LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
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const MachineOperand &MO) const;
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bool runOnce(MachineFunction &MF);
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LaneBitmask determineInitialDefinedLanes(unsigned Reg);
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LaneBitmask determineInitialUsedLanes(unsigned Reg);
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bool isUndefRegAtInput(const MachineOperand &MO,
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const VRegInfo &RegInfo) const;
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bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
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const MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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void PutInWorklist(unsigned RegIdx) {
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if (WorklistMembers.test(RegIdx))
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return;
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WorklistMembers.set(RegIdx);
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Worklist.push_back(RegIdx);
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}
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VRegInfo *VRegInfos;
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/// Worklist containing virtreg indexes.
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std::deque<unsigned> Worklist;
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BitVector WorklistMembers;
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/// This bitvector is set for each vreg index where the vreg is defined
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/// by an instruction where lowersToCopies()==true.
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BitVector DefinedByCopy;
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};
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} // end anonymous namespace
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char DetectDeadLanes::ID = 0;
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char &llvm::DetectDeadLanesID = DetectDeadLanes::ID;
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INITIALIZE_PASS(DetectDeadLanes, DEBUG_TYPE, "Detect Dead Lanes", false, false)
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/// Returns true if \p MI will get lowered to a series of COPY instructions.
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/// We call this a COPY-like instruction.
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static bool lowersToCopies(const MachineInstr &MI) {
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// Note: We could support instructions with MCInstrDesc::isRegSequenceLike(),
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// isExtractSubRegLike(), isInsertSubregLike() in the future even though they
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// are not lowered to a COPY.
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switch (MI.getOpcode()) {
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case TargetOpcode::COPY:
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case TargetOpcode::PHI:
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case TargetOpcode::INSERT_SUBREG:
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case TargetOpcode::REG_SEQUENCE:
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case TargetOpcode::EXTRACT_SUBREG:
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return true;
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}
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return false;
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}
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static bool isCrossCopy(const MachineRegisterInfo &MRI,
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const MachineInstr &MI,
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const TargetRegisterClass *DstRC,
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const MachineOperand &MO) {
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assert(lowersToCopies(MI));
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Register SrcReg = MO.getReg();
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const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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if (DstRC == SrcRC)
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return false;
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unsigned SrcSubIdx = MO.getSubReg();
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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unsigned DstSubIdx = 0;
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switch (MI.getOpcode()) {
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case TargetOpcode::INSERT_SUBREG:
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if (MI.getOperandNo(&MO) == 2)
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DstSubIdx = MI.getOperand(3).getImm();
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break;
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case TargetOpcode::REG_SEQUENCE: {
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unsigned OpNum = MI.getOperandNo(&MO);
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DstSubIdx = MI.getOperand(OpNum+1).getImm();
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break;
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}
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case TargetOpcode::EXTRACT_SUBREG: {
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unsigned SubReg = MI.getOperand(2).getImm();
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SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
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}
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}
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unsigned PreA, PreB; // Unused.
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if (SrcSubIdx && DstSubIdx)
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return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
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PreB);
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if (SrcSubIdx)
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return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
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if (DstSubIdx)
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return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
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return !TRI.getCommonSubClass(SrcRC, DstRC);
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}
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void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
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LaneBitmask UsedLanes) {
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if (!MO.readsReg())
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return;
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Register MOReg = MO.getReg();
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if (!Register::isVirtualRegister(MOReg))
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return;
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unsigned MOSubReg = MO.getSubReg();
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if (MOSubReg != 0)
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UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes);
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UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
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unsigned MORegIdx = Register::virtReg2Index(MOReg);
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VRegInfo &MORegInfo = VRegInfos[MORegIdx];
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LaneBitmask PrevUsedLanes = MORegInfo.UsedLanes;
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// Any change at all?
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if ((UsedLanes & ~PrevUsedLanes).none())
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return;
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// Set UsedLanes and remember instruction for further propagation.
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MORegInfo.UsedLanes = PrevUsedLanes | UsedLanes;
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if (DefinedByCopy.test(MORegIdx))
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PutInWorklist(MORegIdx);
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}
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void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
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LaneBitmask UsedLanes) {
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for (const MachineOperand &MO : MI.uses()) {
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if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
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continue;
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LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
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addUsedLanesOnOperand(MO, UsedOnMO);
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}
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}
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LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
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LaneBitmask UsedLanes,
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const MachineOperand &MO) const {
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unsigned OpNum = MI.getOperandNo(&MO);
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assert(lowersToCopies(MI) &&
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DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
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switch (MI.getOpcode()) {
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case TargetOpcode::COPY:
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case TargetOpcode::PHI:
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return UsedLanes;
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case TargetOpcode::REG_SEQUENCE: {
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assert(OpNum % 2 == 1);
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unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
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return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
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}
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case TargetOpcode::INSERT_SUBREG: {
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unsigned SubIdx = MI.getOperand(3).getImm();
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LaneBitmask MO2UsedLanes =
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TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
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if (OpNum == 2)
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return MO2UsedLanes;
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const MachineOperand &Def = MI.getOperand(0);
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Register DefReg = Def.getReg();
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const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
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LaneBitmask MO1UsedLanes;
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if (RC->CoveredBySubRegs)
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MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
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else
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MO1UsedLanes = RC->LaneMask;
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assert(OpNum == 1);
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return MO1UsedLanes;
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}
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case TargetOpcode::EXTRACT_SUBREG: {
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assert(OpNum == 1);
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unsigned SubIdx = MI.getOperand(2).getImm();
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return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
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}
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default:
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llvm_unreachable("function must be called with COPY-like instruction");
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}
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}
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void DetectDeadLanes::transferDefinedLanesStep(const MachineOperand &Use,
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LaneBitmask DefinedLanes) {
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if (!Use.readsReg())
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return;
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// Check whether the operand writes a vreg and is part of a COPY-like
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// instruction.
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const MachineInstr &MI = *Use.getParent();
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if (MI.getDesc().getNumDefs() != 1)
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return;
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// FIXME: PATCHPOINT instructions announce a Def that does not always exist,
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// they really need to be modeled differently!
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if (MI.getOpcode() == TargetOpcode::PATCHPOINT)
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return;
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const MachineOperand &Def = *MI.defs().begin();
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Register DefReg = Def.getReg();
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if (!Register::isVirtualRegister(DefReg))
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return;
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unsigned DefRegIdx = Register::virtReg2Index(DefReg);
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if (!DefinedByCopy.test(DefRegIdx))
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return;
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unsigned OpNum = MI.getOperandNo(&Use);
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DefinedLanes =
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TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
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DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
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VRegInfo &RegInfo = VRegInfos[DefRegIdx];
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LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
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// Any change at all?
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if ((DefinedLanes & ~PrevDefinedLanes).none())
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return;
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RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes;
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PutInWorklist(DefRegIdx);
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}
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LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def,
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unsigned OpNum, LaneBitmask DefinedLanes) const {
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const MachineInstr &MI = *Def.getParent();
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// Translate DefinedLanes if necessary.
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switch (MI.getOpcode()) {
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case TargetOpcode::REG_SEQUENCE: {
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unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
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DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
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DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
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break;
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}
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case TargetOpcode::INSERT_SUBREG: {
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unsigned SubIdx = MI.getOperand(3).getImm();
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if (OpNum == 2) {
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DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
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DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
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} else {
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assert(OpNum == 1 && "INSERT_SUBREG must have two operands");
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// Ignore lanes defined by operand 2.
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DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
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}
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break;
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}
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case TargetOpcode::EXTRACT_SUBREG: {
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unsigned SubIdx = MI.getOperand(2).getImm();
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assert(OpNum == 1 && "EXTRACT_SUBREG must have one register operand only");
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DefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(SubIdx, DefinedLanes);
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break;
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}
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case TargetOpcode::COPY:
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case TargetOpcode::PHI:
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break;
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default:
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llvm_unreachable("function must be called with COPY-like instruction");
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}
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assert(Def.getSubReg() == 0 &&
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"Should not have subregister defs in machine SSA phase");
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DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
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return DefinedLanes;
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}
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LaneBitmask DetectDeadLanes::determineInitialDefinedLanes(unsigned Reg) {
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|
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// Live-In or unused registers have no definition but are considered fully
|
||
|
|
// defined.
|
||
|
|
if (!MRI->hasOneDef(Reg))
|
||
|
|
return LaneBitmask::getAll();
|
||
|
|
|
||
|
|
const MachineOperand &Def = *MRI->def_begin(Reg);
|
||
|
|
const MachineInstr &DefMI = *Def.getParent();
|
||
|
|
if (lowersToCopies(DefMI)) {
|
||
|
|
// Start optimisatically with no used or defined lanes for copy
|
||
|
|
// instructions. The following dataflow analysis will add more bits.
|
||
|
|
unsigned RegIdx = Register::virtReg2Index(Reg);
|
||
|
|
DefinedByCopy.set(RegIdx);
|
||
|
|
PutInWorklist(RegIdx);
|
||
|
|
|
||
|
|
if (Def.isDead())
|
||
|
|
return LaneBitmask::getNone();
|
||
|
|
|
||
|
|
// COPY/PHI can copy across unrelated register classes (example: float/int)
|
||
|
|
// with incompatible subregister structure. Do not include these in the
|
||
|
|
// dataflow analysis since we cannot transfer lanemasks in a meaningful way.
|
||
|
|
const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
|
||
|
|
|
||
|
|
// Determine initially DefinedLanes.
|
||
|
|
LaneBitmask DefinedLanes;
|
||
|
|
for (const MachineOperand &MO : DefMI.uses()) {
|
||
|
|
if (!MO.isReg() || !MO.readsReg())
|
||
|
|
continue;
|
||
|
|
Register MOReg = MO.getReg();
|
||
|
|
if (!MOReg)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
LaneBitmask MODefinedLanes;
|
||
|
|
if (Register::isPhysicalRegister(MOReg)) {
|
||
|
|
MODefinedLanes = LaneBitmask::getAll();
|
||
|
|
} else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
|
||
|
|
MODefinedLanes = LaneBitmask::getAll();
|
||
|
|
} else {
|
||
|
|
assert(Register::isVirtualRegister(MOReg));
|
||
|
|
if (MRI->hasOneDef(MOReg)) {
|
||
|
|
const MachineOperand &MODef = *MRI->def_begin(MOReg);
|
||
|
|
const MachineInstr &MODefMI = *MODef.getParent();
|
||
|
|
// Bits from copy-like operations will be added later.
|
||
|
|
if (lowersToCopies(MODefMI) || MODefMI.isImplicitDef())
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
unsigned MOSubReg = MO.getSubReg();
|
||
|
|
MODefinedLanes = MRI->getMaxLaneMaskForVReg(MOReg);
|
||
|
|
MODefinedLanes = TRI->reverseComposeSubRegIndexLaneMask(
|
||
|
|
MOSubReg, MODefinedLanes);
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned OpNum = DefMI.getOperandNo(&MO);
|
||
|
|
DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
|
||
|
|
}
|
||
|
|
return DefinedLanes;
|
||
|
|
}
|
||
|
|
if (DefMI.isImplicitDef() || Def.isDead())
|
||
|
|
return LaneBitmask::getNone();
|
||
|
|
|
||
|
|
assert(Def.getSubReg() == 0 &&
|
||
|
|
"Should not have subregister defs in machine SSA phase");
|
||
|
|
return MRI->getMaxLaneMaskForVReg(Reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
|
||
|
|
LaneBitmask UsedLanes = LaneBitmask::getNone();
|
||
|
|
for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
|
||
|
|
if (!MO.readsReg())
|
||
|
|
continue;
|
||
|
|
|
||
|
|
const MachineInstr &UseMI = *MO.getParent();
|
||
|
|
if (UseMI.isKill())
|
||
|
|
continue;
|
||
|
|
|
||
|
|
unsigned SubReg = MO.getSubReg();
|
||
|
|
if (lowersToCopies(UseMI)) {
|
||
|
|
assert(UseMI.getDesc().getNumDefs() == 1);
|
||
|
|
const MachineOperand &Def = *UseMI.defs().begin();
|
||
|
|
Register DefReg = Def.getReg();
|
||
|
|
// The used lanes of COPY-like instruction operands are determined by the
|
||
|
|
// following dataflow analysis.
|
||
|
|
if (Register::isVirtualRegister(DefReg)) {
|
||
|
|
// But ignore copies across incompatible register classes.
|
||
|
|
bool CrossCopy = false;
|
||
|
|
if (lowersToCopies(UseMI)) {
|
||
|
|
const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
|
||
|
|
CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
|
||
|
|
if (CrossCopy)
|
||
|
|
LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!CrossCopy)
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Shortcut: All lanes are used.
|
||
|
|
if (SubReg == 0)
|
||
|
|
return MRI->getMaxLaneMaskForVReg(Reg);
|
||
|
|
|
||
|
|
UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
|
||
|
|
}
|
||
|
|
return UsedLanes;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
|
||
|
|
const VRegInfo &RegInfo) const {
|
||
|
|
unsigned SubReg = MO.getSubReg();
|
||
|
|
LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
|
||
|
|
return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none();
|
||
|
|
}
|
||
|
|
|
||
|
|
bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
|
||
|
|
bool *CrossCopy) const {
|
||
|
|
if (!MO.isUse())
|
||
|
|
return false;
|
||
|
|
const MachineInstr &MI = *MO.getParent();
|
||
|
|
if (!lowersToCopies(MI))
|
||
|
|
return false;
|
||
|
|
const MachineOperand &Def = MI.getOperand(0);
|
||
|
|
Register DefReg = Def.getReg();
|
||
|
|
if (!Register::isVirtualRegister(DefReg))
|
||
|
|
return false;
|
||
|
|
unsigned DefRegIdx = Register::virtReg2Index(DefReg);
|
||
|
|
if (!DefinedByCopy.test(DefRegIdx))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
|
||
|
|
LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
|
||
|
|
if (UsedLanes.any())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
Register MOReg = MO.getReg();
|
||
|
|
if (Register::isVirtualRegister(MOReg)) {
|
||
|
|
const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
|
||
|
|
*CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
|
||
|
|
}
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool DetectDeadLanes::runOnce(MachineFunction &MF) {
|
||
|
|
// First pass: Populate defs/uses of vregs with initial values
|
||
|
|
unsigned NumVirtRegs = MRI->getNumVirtRegs();
|
||
|
|
for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
|
||
|
|
unsigned Reg = Register::index2VirtReg(RegIdx);
|
||
|
|
|
||
|
|
// Determine used/defined lanes and add copy instructions to worklist.
|
||
|
|
VRegInfo &Info = VRegInfos[RegIdx];
|
||
|
|
Info.DefinedLanes = determineInitialDefinedLanes(Reg);
|
||
|
|
Info.UsedLanes = determineInitialUsedLanes(Reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Iterate as long as defined lanes/used lanes keep changing.
|
||
|
|
while (!Worklist.empty()) {
|
||
|
|
unsigned RegIdx = Worklist.front();
|
||
|
|
Worklist.pop_front();
|
||
|
|
WorklistMembers.reset(RegIdx);
|
||
|
|
VRegInfo &Info = VRegInfos[RegIdx];
|
||
|
|
unsigned Reg = Register::index2VirtReg(RegIdx);
|
||
|
|
|
||
|
|
// Transfer UsedLanes to operands of DefMI (backwards dataflow).
|
||
|
|
MachineOperand &Def = *MRI->def_begin(Reg);
|
||
|
|
const MachineInstr &MI = *Def.getParent();
|
||
|
|
transferUsedLanesStep(MI, Info.UsedLanes);
|
||
|
|
// Transfer DefinedLanes to users of Reg (forward dataflow).
|
||
|
|
for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
|
||
|
|
transferDefinedLanesStep(MO, Info.DefinedLanes);
|
||
|
|
}
|
||
|
|
|
||
|
|
LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0;
|
||
|
|
RegIdx < NumVirtRegs;
|
||
|
|
++RegIdx) {
|
||
|
|
unsigned Reg = Register::index2VirtReg(RegIdx);
|
||
|
|
const VRegInfo &Info = VRegInfos[RegIdx];
|
||
|
|
dbgs() << printReg(Reg, nullptr)
|
||
|
|
<< " Used: " << PrintLaneMask(Info.UsedLanes)
|
||
|
|
<< " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
|
||
|
|
} dbgs() << "\n";);
|
||
|
|
|
||
|
|
bool Again = false;
|
||
|
|
// Mark operands as dead/unused.
|
||
|
|
for (MachineBasicBlock &MBB : MF) {
|
||
|
|
for (MachineInstr &MI : MBB) {
|
||
|
|
for (MachineOperand &MO : MI.operands()) {
|
||
|
|
if (!MO.isReg())
|
||
|
|
continue;
|
||
|
|
Register Reg = MO.getReg();
|
||
|
|
if (!Register::isVirtualRegister(Reg))
|
||
|
|
continue;
|
||
|
|
unsigned RegIdx = Register::virtReg2Index(Reg);
|
||
|
|
const VRegInfo &RegInfo = VRegInfos[RegIdx];
|
||
|
|
if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
|
||
|
|
LLVM_DEBUG(dbgs()
|
||
|
|
<< "Marking operand '" << MO << "' as dead in " << MI);
|
||
|
|
MO.setIsDead();
|
||
|
|
}
|
||
|
|
if (MO.readsReg()) {
|
||
|
|
bool CrossCopy = false;
|
||
|
|
if (isUndefRegAtInput(MO, RegInfo)) {
|
||
|
|
LLVM_DEBUG(dbgs()
|
||
|
|
<< "Marking operand '" << MO << "' as undef in " << MI);
|
||
|
|
MO.setIsUndef();
|
||
|
|
} else if (isUndefInput(MO, &CrossCopy)) {
|
||
|
|
LLVM_DEBUG(dbgs()
|
||
|
|
<< "Marking operand '" << MO << "' as undef in " << MI);
|
||
|
|
MO.setIsUndef();
|
||
|
|
if (CrossCopy)
|
||
|
|
Again = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return Again;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
|
||
|
|
// Don't bother if we won't track subregister liveness later. This pass is
|
||
|
|
// required for correctness if subregister liveness is enabled because the
|
||
|
|
// register coalescer cannot deal with hidden dead defs. However without
|
||
|
|
// subregister liveness enabled, the expected benefits of this pass are small
|
||
|
|
// so we safe the compile time.
|
||
|
|
MRI = &MF.getRegInfo();
|
||
|
|
if (!MRI->subRegLivenessEnabled()) {
|
||
|
|
LLVM_DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
TRI = MRI->getTargetRegisterInfo();
|
||
|
|
|
||
|
|
unsigned NumVirtRegs = MRI->getNumVirtRegs();
|
||
|
|
VRegInfos = new VRegInfo[NumVirtRegs];
|
||
|
|
WorklistMembers.resize(NumVirtRegs);
|
||
|
|
DefinedByCopy.resize(NumVirtRegs);
|
||
|
|
|
||
|
|
bool Again;
|
||
|
|
do {
|
||
|
|
Again = runOnce(MF);
|
||
|
|
} while(Again);
|
||
|
|
|
||
|
|
DefinedByCopy.clear();
|
||
|
|
WorklistMembers.clear();
|
||
|
|
delete[] VRegInfos;
|
||
|
|
return true;
|
||
|
|
}
|