366 lines
12 KiB
C++
366 lines
12 KiB
C++
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//===- MCSubtargetInfo.cpp - Subtarget Information ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <cstring>
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using namespace llvm;
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/// Find KV in array using binary search.
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template <typename T>
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static const T *Find(StringRef S, ArrayRef<T> A) {
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// Binary search the array
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auto F = llvm::lower_bound(A, S);
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// If not found then return NULL
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if (F == A.end() || StringRef(F->Key) != S) return nullptr;
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// Return the found array item
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return F;
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}
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/// For each feature that is (transitively) implied by this feature, set it.
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static
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void SetImpliedBits(FeatureBitset &Bits, const FeatureBitset &Implies,
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ArrayRef<SubtargetFeatureKV> FeatureTable) {
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// OR the Implies bits in outside the loop. This allows the Implies for CPUs
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// which might imply features not in FeatureTable to use this.
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Bits |= Implies;
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for (const SubtargetFeatureKV &FE : FeatureTable)
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if (Implies.test(FE.Value))
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SetImpliedBits(Bits, FE.Implies.getAsBitset(), FeatureTable);
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}
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/// For each feature that (transitively) implies this feature, clear it.
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static
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void ClearImpliedBits(FeatureBitset &Bits, unsigned Value,
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ArrayRef<SubtargetFeatureKV> FeatureTable) {
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for (const SubtargetFeatureKV &FE : FeatureTable) {
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if (FE.Implies.getAsBitset().test(Value)) {
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Bits.reset(FE.Value);
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ClearImpliedBits(Bits, FE.Value, FeatureTable);
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}
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}
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}
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static void ApplyFeatureFlag(FeatureBitset &Bits, StringRef Feature,
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ArrayRef<SubtargetFeatureKV> FeatureTable) {
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assert(SubtargetFeatures::hasFlag(Feature) &&
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"Feature flags should start with '+' or '-'");
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// Find feature in table.
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const SubtargetFeatureKV *FeatureEntry =
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Find(SubtargetFeatures::StripFlag(Feature), FeatureTable);
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// If there is a match
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if (FeatureEntry) {
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// Enable/disable feature in bits
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if (SubtargetFeatures::isEnabled(Feature)) {
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Bits.set(FeatureEntry->Value);
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// For each feature that this implies, set it.
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SetImpliedBits(Bits, FeatureEntry->Implies.getAsBitset(), FeatureTable);
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} else {
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Bits.reset(FeatureEntry->Value);
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// For each feature that implies this, clear it.
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ClearImpliedBits(Bits, FeatureEntry->Value, FeatureTable);
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}
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} else {
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errs() << "'" << Feature << "' is not a recognized feature for this target"
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<< " (ignoring feature)\n";
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}
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}
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/// Return the length of the longest entry in the table.
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template <typename T>
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static size_t getLongestEntryLength(ArrayRef<T> Table) {
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size_t MaxLen = 0;
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for (auto &I : Table)
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MaxLen = std::max(MaxLen, std::strlen(I.Key));
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return MaxLen;
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}
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/// Display help for feature and mcpu choices.
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static void Help(ArrayRef<SubtargetSubTypeKV> CPUTable,
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ArrayRef<SubtargetFeatureKV> FeatTable) {
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// the static variable ensures that the help information only gets
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// printed once even though a target machine creates multiple subtargets
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static bool PrintOnce = false;
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if (PrintOnce) {
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return;
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}
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// Determine the length of the longest CPU and Feature entries.
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unsigned MaxCPULen = getLongestEntryLength(CPUTable);
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unsigned MaxFeatLen = getLongestEntryLength(FeatTable);
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// Print the CPU table.
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errs() << "Available CPUs for this target:\n\n";
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for (auto &CPU : CPUTable)
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errs() << format(" %-*s - Select the %s processor.\n", MaxCPULen, CPU.Key,
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CPU.Key);
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errs() << '\n';
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// Print the Feature table.
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errs() << "Available features for this target:\n\n";
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for (auto &Feature : FeatTable)
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errs() << format(" %-*s - %s.\n", MaxFeatLen, Feature.Key, Feature.Desc);
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errs() << '\n';
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errs() << "Use +feature to enable a feature, or -feature to disable it.\n"
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"For example, llc -mcpu=mycpu -mattr=+feature1,-feature2\n";
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PrintOnce = true;
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}
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/// Display help for mcpu choices only
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static void cpuHelp(ArrayRef<SubtargetSubTypeKV> CPUTable) {
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// the static variable ensures that the help information only gets
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// printed once even though a target machine creates multiple subtargets
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static bool PrintOnce = false;
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if (PrintOnce) {
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return;
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}
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// Print the CPU table.
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errs() << "Available CPUs for this target:\n\n";
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for (auto &CPU : CPUTable)
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errs() << "\t" << CPU.Key << "\n";
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errs() << '\n';
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errs() << "Use -mcpu or -mtune to specify the target's processor.\n"
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"For example, clang --target=aarch64-unknown-linux-gui "
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"-mcpu=cortex-a35\n";
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PrintOnce = true;
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}
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static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
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ArrayRef<SubtargetSubTypeKV> ProcDesc,
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ArrayRef<SubtargetFeatureKV> ProcFeatures) {
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SubtargetFeatures Features(FS);
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if (ProcDesc.empty() || ProcFeatures.empty())
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return FeatureBitset();
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assert(llvm::is_sorted(ProcDesc) && "CPU table is not sorted");
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assert(llvm::is_sorted(ProcFeatures) && "CPU features table is not sorted");
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// Resulting bits
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FeatureBitset Bits;
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// Check if help is needed
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if (CPU == "help")
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Help(ProcDesc, ProcFeatures);
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// Find CPU entry if CPU name is specified.
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else if (!CPU.empty()) {
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const SubtargetSubTypeKV *CPUEntry = Find(CPU, ProcDesc);
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// If there is a match
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if (CPUEntry) {
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// Set the features implied by this CPU feature, if any.
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SetImpliedBits(Bits, CPUEntry->Implies.getAsBitset(), ProcFeatures);
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} else {
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errs() << "'" << CPU << "' is not a recognized processor for this target"
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<< " (ignoring processor)\n";
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}
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}
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if (!TuneCPU.empty()) {
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const SubtargetSubTypeKV *CPUEntry = Find(TuneCPU, ProcDesc);
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// If there is a match
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if (CPUEntry) {
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// Set the features implied by this CPU feature, if any.
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SetImpliedBits(Bits, CPUEntry->TuneImplies.getAsBitset(), ProcFeatures);
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} else if (TuneCPU != CPU) {
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errs() << "'" << TuneCPU << "' is not a recognized processor for this "
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<< "target (ignoring processor)\n";
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}
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}
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// Iterate through each feature
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for (const std::string &Feature : Features.getFeatures()) {
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// Check for help
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if (Feature == "+help")
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Help(ProcDesc, ProcFeatures);
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else if (Feature == "+cpuhelp")
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cpuHelp(ProcDesc);
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else
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ApplyFeatureFlag(Bits, Feature, ProcFeatures);
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}
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return Bits;
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}
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void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU,
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StringRef FS) {
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FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
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if (!TuneCPU.empty())
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CPUSchedModel = &getSchedModelForCPU(TuneCPU);
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else
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CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
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}
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void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU,
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StringRef FS) {
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FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
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}
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MCSubtargetInfo::MCSubtargetInfo(const Triple &TT, StringRef C, StringRef TC,
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StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
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ArrayRef<SubtargetSubTypeKV> PD,
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const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL,
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const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC,
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const unsigned *FP)
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: TargetTriple(TT), CPU(std::string(C)), TuneCPU(std::string(TC)),
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ProcFeatures(PF), ProcDesc(PD), WriteProcResTable(WPR),
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WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS),
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OperandCycles(OC), ForwardingPaths(FP) {
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InitMCProcessorInfo(CPU, TuneCPU, FS);
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
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FeatureBits.flip(FB);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
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FeatureBits ^= FB;
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::SetFeatureBitsTransitively(
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const FeatureBitset &FB) {
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SetImpliedBits(FeatureBits, FB, ProcFeatures);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ClearFeatureBitsTransitively(
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const FeatureBitset &FB) {
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for (unsigned I = 0, E = FB.size(); I < E; I++) {
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if (FB[I]) {
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FeatureBits.reset(I);
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ClearImpliedBits(FeatureBits, I, ProcFeatures);
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}
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}
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef Feature) {
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// Find feature in table.
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const SubtargetFeatureKV *FeatureEntry =
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Find(SubtargetFeatures::StripFlag(Feature), ProcFeatures);
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// If there is a match
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if (FeatureEntry) {
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if (FeatureBits.test(FeatureEntry->Value)) {
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FeatureBits.reset(FeatureEntry->Value);
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// For each feature that implies this, clear it.
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ClearImpliedBits(FeatureBits, FeatureEntry->Value, ProcFeatures);
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} else {
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FeatureBits.set(FeatureEntry->Value);
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// For each feature that this implies, set it.
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SetImpliedBits(FeatureBits, FeatureEntry->Implies.getAsBitset(),
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ProcFeatures);
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}
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} else {
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errs() << "'" << Feature << "' is not a recognized feature for this target"
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<< " (ignoring feature)\n";
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}
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
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::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
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return FeatureBits;
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}
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bool MCSubtargetInfo::checkFeatures(StringRef FS) const {
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SubtargetFeatures T(FS);
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FeatureBitset Set, All;
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for (std::string F : T.getFeatures()) {
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::ApplyFeatureFlag(Set, F, ProcFeatures);
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if (F[0] == '-')
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F[0] = '+';
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::ApplyFeatureFlag(All, F, ProcFeatures);
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}
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return (FeatureBits & All) == Set;
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}
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const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
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assert(llvm::is_sorted(ProcDesc) &&
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"Processor machine model table is not sorted");
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// Find entry
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const SubtargetSubTypeKV *CPUEntry = Find(CPU, ProcDesc);
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if (!CPUEntry) {
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if (CPU != "help") // Don't error if the user asked for help.
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errs() << "'" << CPU
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<< "' is not a recognized processor for this target"
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<< " (ignoring processor)\n";
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return MCSchedModel::GetDefaultSchedModel();
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}
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assert(CPUEntry->SchedModel && "Missing processor SchedModel value");
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return *CPUEntry->SchedModel;
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}
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InstrItineraryData
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MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
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const MCSchedModel &SchedModel = getSchedModelForCPU(CPU);
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return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
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}
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void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
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InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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ForwardingPaths);
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}
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Optional<unsigned> MCSubtargetInfo::getCacheSize(unsigned Level) const {
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return Optional<unsigned>();
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}
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Optional<unsigned>
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MCSubtargetInfo::getCacheAssociativity(unsigned Level) const {
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return Optional<unsigned>();
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}
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Optional<unsigned> MCSubtargetInfo::getCacheLineSize(unsigned Level) const {
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return Optional<unsigned>();
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}
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unsigned MCSubtargetInfo::getPrefetchDistance() const {
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return 0;
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}
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unsigned MCSubtargetInfo::getMaxPrefetchIterationsAhead() const {
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return UINT_MAX;
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}
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bool MCSubtargetInfo::enableWritePrefetching() const {
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return false;
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}
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unsigned MCSubtargetInfo::getMinPrefetchStride(unsigned NumMemAccesses,
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unsigned NumStridedMemAccesses,
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unsigned NumPrefetches,
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bool HasCall) const {
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return 1;
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}
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