51 lines
2.0 KiB
LLVM
51 lines
2.0 KiB
LLVM
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa,+slow-misaligned-128store -enable-misched -verify-misched -o - | FileCheck %s
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; Tests to check that the scheduler dependencies derived from alias analysis are
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; correct when we have loads that have been split up so that they can later be
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; merged into STP.
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; Now that overwritten stores are elided in SelectionDAG, dependencies
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; are resolved and removed before MISCHED. Check that we have
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; equivalent pair of stp calls as a baseline.
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; CHECK-LABEL: test_splat
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; CHECK: ldr [[REG:w[0-9]+]], [x2]
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; CHECK-DAG: stp w0, [[REG]], [x2, #12]
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; CHECK-DAG: stp [[REG]], w1, [x2, #4]
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define void @test_splat(i32 %x, i32 %y, i32* %p) {
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entry:
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%val = load i32, i32* %p, align 4
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%0 = getelementptr inbounds i32, i32* %p, i64 1
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%1 = getelementptr inbounds i32, i32* %p, i64 2
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%2 = getelementptr inbounds i32, i32* %p, i64 3
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%vec0 = insertelement <4 x i32> undef, i32 %val, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %val, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %val, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %val, i32 3
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%3 = bitcast i32* %0 to <4 x i32>*
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store <4 x i32> %vec3, <4 x i32>* %3, align 4
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store i32 %x, i32* %2, align 4
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store i32 %y, i32* %1, align 4
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ret void
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}
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1)
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%struct.tree_common = type { i8*, i8*, i32 }
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; CHECK-LABEL: test_zero
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; CHECK-DAG: stp x2, xzr, [x0, #8]
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; CHECK-DAG: str w1, [x0, #16]
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; CHECK-DAG: str xzr, [x0]
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define void @test_zero(%struct.tree_common* %t, i32 %code, i8* %type) {
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entry:
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%0 = bitcast %struct.tree_common* %t to i8*
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tail call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 24, i1 false)
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%code1 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 2
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store i32 %code, i32* %code1, align 8
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%type2 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 1
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store i8* %type, i8** %type2, align 8
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ret void
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}
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